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參數(shù)資料
| 型號： | S19237PB13 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封裝： | PLASTIC, BGA-255 |
| 文件頁數(shù)： | 9/60頁 |
| 文件大?。?/td> | 1418K |
| 代理商： | S19237PB13 |
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S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
AMCC Confidential and Proprietary
DS1454
17
Data Sheet
the recovered POCLK is fed into the phase detector
block. The output of the phase detector block is fed
into the external loop filter and VCO. The output of the
external VCO is fed into the CSU_IN input, which
would be selected as the reference clock for the CSU
block. The jitter transfer specification, as defined in
GR-253-CORE, is met in this mode.
Case 2. XVCO select input is inactive. When LLEB
input is active and XVCO input is inactive, the internal
recovered serial clock (RSCLK) acts as the timing
source for the CSU block. In this case, the output of
the phase detector block is not used. The jitter transfer
specification, as defined in GR-253-CORE, is not met
in this mode.
This mode allows the network to be isolated from the
digit a l side of t h e n ode (fram e r/map per get s
bypassed).
See Table 9, Line Loopback Enable Mode. This input
is only accessible through the MDIO bus register.
The BOLD CELLS denote the default state
Serial Loop Timing (SLPTIME) – MDIO Register
This active high input selects the serial loop timing
mode. In this mode, the transmitter parallel-to-serial
converter will utilize the internal RSCLK from the
receiver rather than the CSU output clock (TXCLK).
The outgoing POCLK provides the timing for the
receive section of the framer/mapper. Since some
framer/mappers operate with a fixed-size internal
FIFO, the framer/mappers transmit section will have to
be synchronized with its receive section in order to
avoid over/under flowing of the internal FIFO. In SLP-
TIME mode, the transmit clock, or PCLK, is generated
from the internal RSCLK, the same clock that gener-
ates PO CLK. Th e tran sce iver ’s inte rnal clock
synthesizer circuit (CSU Block shown in Figure 5) is
bypassed in this configuration, providing an alternate
path for system-level timing/jitter analysis.
SLPTIME mode will take precedence over the RLP-
TIME mode if both these modes are active at the same
time. The XVCO input must be programmed to logic
low in the SLPTIME mode. This will disable the exter-
nal VCO mode. The external VCO will never be used
in the SLPTIME mode.
The jitter transfer specification, as defined in GR-253-
CORE, is not met in the SLPTIME mode. See Table
details. This input is only accessible through the MDIO
bus register.
Reference Loop Timing (RLPTIME) – MDIO Register
This active high input selects the reference loop timing
mode. In this mode, the transmitter CSU utilizes the
receiver POCLK instead of the transmitter external ref-
erence clock (CSU_REFCLK). High-speed data flows
into the receiver section of the transceiver and is dese-
rialized and aligned before being transmitted to the
framer/mapper. The transmitted POCLK provides the
timing for the receive section of the framer/mapper.
Since some framer/mappers operate with a fixed-size
internal FIFO, the framer/mapper transmit section will
have to be synchronized with its receive section to
avoid over/under flowing of the internal FIFO. In RLP-
TIME mode, the transmit clock, or PCLK, is generated
from the outbound POCLK with the use of the trans-
ceiver’s internal clock synthesizer unit.
The SLPTIME mode must be inactive for the RLP-
TIME mode to be active. The SLPTIME mode, if
active, will take precedence over the RLPTIME mode.
XVCO select input must be programmed to logic high
in the RLPTIME mode. This enables the external VCO
which must be used in the RLPTIME mode.
In the RLPTIME mode, the internal POCLK is fed into
the phase detector block. The output of the phase
detector block is fed into the external VCO. The output
of the external VCO then goes into the CSU_IN input
which acts as the reference clock for the internal clock
synthesizer circuit (CSU block in Figure 5). The jitter
transfer specification, as defined in GR-253-CORE, is
met in this mode. See Table 10, Serial and Reference
Loopback Enable, for details. This input is only acces-
sible through the MDIO bus register.
Table 9. Line Loopback Enable Mode
LLEB
Mode of Operation/ Clock Source
0
Line Loopback Active. Internal RSCLK will
be the timing source for the transmitter if
XVCO input is inactive.
0
Line Loopback Active. POCLK (Output of
the external XVCO that is fed into the
CSU_IN input) will be the timing source for
the transmitter if XVCO input is active.
1
Line Loopback inactive.
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相關代理商/技術參數(shù) |
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| S19237PB13-2 | 制造商:AppliedMicro 功能描述: |
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