參數(shù)資料
型號： S19237PB13
廠商： APPLIEDMICRO INC
元件分類： 數(shù)字傳輸電路
英文描述： TRANSCEIVER, PBGA255
封裝： PLASTIC, BGA-255
文件頁數(shù)： 19/60頁
文件大小： 1418K
代理商： S19237PB13
26
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
SONET Jitter Generation
The following jitter generation requirement applies to
STS-192 interfaces as defined in GR-253-CORE.
According to GR-253-CORE, jitter generation shall
not exceed 0.10 UIPP for STS-192 interfaces when
measured using a bandpass measurement filter
with a high-pass cutoff frequency of 50 kHz and a
low-pass cutoff frequency of at least B3 = 80 MHz.
Note that for SONET rates up to STS-48, the cur-
rent jitter generation requirement in GR-253-CORE
states that the generated jitter must be less than
0.01 UI rms and 0.10 UIPP. At the STS-192 rate,
the measurement of RMS phase variations with
less than 0.01 UI granularity (1 picosecond) may
not be feasible. Therefore, this requirement speci-
fies the jitter generation only in terms of 0.10 UIPP.
The S19237 meets the Telecordia Jitter Generation
Specification by having a worst-case jitter generation
of 3 mUIRMS in the normal mode of operation.
10 Gigabit Ethernet Jitter Tolerance
The following 10 Gigabit Ethernet jitter tolerance
requirement applies to 10GBASE-ER as defined in
IEEE Draft P802.3ae/D4.0. This total jitter is com-
posed of three components: deterministic jitter;
random jitter; and an additional sinusoidal jitter.
The three fundamental components of Jitter Tolerance
testing are:
Input Jitter (Dj and Rj)
Sinusoidal Jitter
Test Pattern (Test patterns are different for
10GBASE-R and 10GBASE-W)
Input Jitter (amount of Dj and Rj)
Dj: 0.35 UI pk-pk
Rj: 0.015 UI rms
The random jitter (RJ) component of the input signal
has uniform spectral content over the measurement
frequency range of at least 1 MHz to 1 GHz per sec-
tion 52.8.2.1 of IEEE Draft P802.3ae/D4.0. Input
Signal must pass the bathtub curves between BERs of
10-6 and 10-12 as shown in Figure 8.
The input jitter used to test receiver jitter tolerance is
specified by the receiver input jitter mask defined in by
the following equations (W and sigma are Dj and Rj
respectively):
Where:
Sinusoidal Jitter
The Sj applied for tolerance testing is defined by the
jitter mask shown in Figure 9 and Table 14 (per section
52.8.2.2 of IEEE Draft P802.3ae/D4.0). The Loop
Bandwidth (LB) for S19237 is approximately 8 MHz.
Test Pattern
Test pattern is chosen per IEEE Draft P802.3ae/D4.0
Section 52.8.2. The test pattern is a static pattern and
can be loaded into a BERT. IEEE Draft P802.3ae/D4.0
specifies two pseudo-random test patterns for
10GBASE-ER testing. One pattern represents typical
scrambled data while the other represents a less typi-
cal pattern which could happen by chance and is
thought to be more demanding of the transmission
process including the clock recovery sub-system. Both
patterns are balanced over their length of 33792 bits.
Test pattern is constructed from 4 Segments
1 segment is constructed with 128 Blocks
1 block is 2 Sync Bits and 64 Payload Bits
Pay load bits are generated with the scrambler
shown in Figure 10.
Scrambler seeded per Tables 15 and 16.
Data input is set to 1 or 0.
Log
10 BER
() AB t 0.5W
–
σ
--------------------
2
–
≥
Log
10 BER
() AB 1 t
–0.5W
–
σ
-----------------------------
2
–
≥
A
1.75 B
Log10 e
()
2
------------------------
0.217
=
,
–
=
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