參數(shù)資料
型號(hào)： S19237PB13
廠商： APPLIEDMICRO INC
元件分類： 數(shù)字傳輸電路
英文描述： TRANSCEIVER, PBGA255
封裝： PLASTIC, BGA-255
文件頁(yè)數(shù)： 16/60頁(yè)
文件大?。?/td> 1418K
代理商： S19237PB13
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
AMCC Confidential and Proprietary
DS1454
23
Data Sheet
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum tol-
erance proposed for SONET equipment by the
Telecordia standard.
Receive Lock Detect
The S19237 contains a lock detect circuit that moni-
tors the integrity of the serial data inputs. If the
received serial data fails the frequency test, the PLL
will be forced to lock to the local reference clock. This
will maintain the correct frequency of the recovered
clock output under loss-of-signal or loss-of-lock condi-
tions. If the recovered clock frequency deviates from
the local reference clock frequency by more than the
typical value stated in Table 22, Performance Specifi-
cations, the PLL will be declared out of lock. The lock
detect circuit will poll the input data stream in an
attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within the typical
the PLL will be declared in lock and the lock detect
output will go active. An inactive SDLVCMOS will also
cause an out-of-lock condition. The receive lock detect
output should not be used as a frequency discrimina-
tor for out of band signals.
Serial-to-Parallel Converter
The serial-to-parallel converter consists of three 16-bit
registers. The first is a serial-in, parallel-out shift regis-
ter, which performs serial-to-parallel conversion. The
second is a 16-bit internal holding register, which
transfers data from the serial-to-parallel register on
byte boundaries. On the falling edge of the POCLK,
the data in the holding register is transferred to an out-
put holding register which drives POUTP/N[15:0].
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is low, a loopback from the transmitter to the receiver
at the serial data rate can be set up for diagnostic pur-
poses. The differential serial output data from the
transmitter is routed to the CRU block in place of the
normal data stream (RSD). The Transmit Serial Data
Output TSDP/N is accessible in the DLEB mode.
DLEB takes precedence over SDLVCMOS.
Receive Built-In Self Test Mode
The S19237 circuitry includes a PRBS generator and
a checker. The receive built-in self test allows for the
verification of the parallel input and output data paths
in the S19237. The S19237 goes in the receive BIST
mode when RX_BIST_EN is programmed to logic
high.
Once the S19237 is in the receive BIST mode, the
PRBS generator will start sending the pattern through
the parallel output data path. The pattern can be a
PRBS pattern or a user defined pattern depending
upon the PRBS_SELECT[1:0] settings. See Table 11
for details. The user defined pattern can be loaded
through the BIST_PTRN[15:0] register. There are two
modes of receive BIST operation:
1. Normal operation with LLEB disabled
2. Normal operation with LLEB enabled
When the line loopback mode is not active, the parallel
output data (POUTP/N[15:0]) must be looped back
externally into the parallel input (PINP/N[15:0]) for the
receive PRBS checker to work with the receive PRBS
generator. If the line loopback mode is enabled, the
POUTP/N[15:0] outputs will be internally looped back
into the PINP/N[15:0] inputs.
Once the RX_BIST_EN input is programmed to logic
high, the receive PRBS checker will be activated but
will not start checking for the valid data pattern until
TX_LOCKDET is active. This ensures that valid data is
being passed through the receive channel. Once the
TX_LOCKDET is active, the checker will begin its ini-
tialization phase for 15 CRU_REFCLK cycles. The
receive checker reads the parallel data output and fig-
ures out the next pattern in the initialization phase.
After the checker is initialized, it will compare the par-
allel data input with the calculated pattern. If the
parallel data input does not match the calculated pat-
tern, the RX_BIST_ERR flag will be set active and the
number of errors will start accumulating on the
BER_COUNT[9:0] register. The bit error rate range
can be selected with the appropriate setting of the
BER_SELECT[1:0]. See Table 12 for details of setting
the range for bit error rate.
The RX_BIST_ERR flag can be cleared by asserting
RX_BIST_CLR in the RX_BIST_EN mode or by reset-
ting (RSTB) the S19237. Once the RX_BIST_CLR
signal has been received by the checker, it will go back
to the initialization phase. RX_BIST_CLR is an active
high level sensitive input. In order for the checker to
clear the RX_BIST_ERR flag, the RX_BIST_CLR
must be asserted high.
Also the BER_R ST B in put re giste r r e se ts th e
BER_OUT[9:0] after each terminal count. BER_RSTB
is a active high input. When active BER_OUT[9:0] is
not reset after each terminal count, but instead contin-
ues to accrue errors. When inactive, BER_OUT[9:0] is
reset to zero error value after each terminal count. The
TERM_COUNT output monitors for the terminal count
of the PRBS checker. The terminal count is set by the
BER_SELECT[1:0] register. See Table 12 for details.
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