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參數(shù)資料
| 型號(hào)： | S19237PB13 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封裝： | PLASTIC, BGA-255 |
| 文件頁數(shù)： | 60/60頁 |
| 文件大?。?/td> | 1418K |
| 代理商： | S19237PB13 |
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S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
AMCC Confidential and Proprietary
DS1454
9
Data Sheet
TRANSMIT INPUT PIN DESCRIPTION
Parallel Input Data (PINP/N[15:0]) – External Pin
PINP/N[15:0] is the LVDS parallel data input bus which
is multiplexed 16:1 and transmitted serially at STS-
192/10 Gigabit Ethernet rates. This data is aligned
with the Parallel Input Clock (PICLKP/N). Bit 15 is the
Most Significant Bit (MSB). This bus is typically con-
nected to a framer, mapper or digital wrapper (e.g.
GANGES, or HUDSON). These inputs are internally
terminated 100
line-to-line but not internally biased.
Parallel Input Clock (PICLKP/N) – External Pin
PICLKP/N is the LVDS 622.08 MHz (or equivalent FEC/
10 Gigabit Ethernet Rate) input clock to which the Par-
allel Input Data (PINP/N[15:0]) is aligned. PICLKP/N is
a delayed version of the PCLK. This clock is used to
clock the data into the S19237 FIFO. These inputs are
internally terminated 100 line-to-line but not internally
biased.
CSU Ref. Clock (CSU_REFCLKP/N) – External Pin
The diff erential REFCLK CML 155. 52 MHz or
622.08 MHz (or equivalent FEC/10 Gigabit Ethernet
Rate) Reference Clock (CSU_REFCLKP/N) input is
used to drive the clock synthesizer Phase Lock Loop
( P LL ) . Se e Ta b l e 1, Re fer enc e Fre q u e n cy
(CSU_REFCLK) for the Clock Synthesis Unit and for
the recommended FEC rates. The CSU_REFCLKP/N
input may go into the Phase Detector (PD) block
shown in Figure 5. The output of the PD block
(PD_UP/PD_DOWN) can be fed into an External filter
and Voltage Controlled Oscillator (VCO) to clean up
the CSU_REFCLKP/N for improved jitter generation.
The output of the external VCO is fed into the CSU_IN
input. The CSU_IN will act as the reference clock for
the CSU block if XVCO select input is active. Table 1
summarizes the increased CSU_REFCLK rates
required for FEC/10GB Ethernet operation. The
S19237 incorporates the bandwidth expansion
requirements needed for the FEC applications that
provide up to eight bytes of correction for a 255 byte
block. Increased CSU_REFCLK frequency is required
for bandwidth expansion due to code words and
Frame Synchronization Byte (FSB). This input is inter-
nally biased and terminated and must be AC coupled.
The BOLD CELLS denote the default state
Table 1. Reference Frequency (CSU_REFCLK) for the Clock Synthesis Unit
REFSEL
Error Correcting Capability Per
255-Byte Block
Percentage Bandwidth Expansion
Due to Code Words and Frame
Synchronization Byte (FSB)
Serial Data
Output (TSD)
Frequency
Required
(CSU_REFCL
K) Frequency
0
STS-192, 0 bytes
0% increase
9.953 Gbps
155.52 MHz
STS-192, Reed Soloman - 255/238
7.14% increase
10.664 Gbps
166.63 MHz
STS-192, Reed Soloman - 255/237
7.59% increase
10.709 Gbps
167.33 MHz
10 Gigabit Ethernet
0% increase
10.000 Gbps
156.25 MHz
10 Gigabit Ethernet 64/66B Encoded
3.125% increase
10.3125 Gbps
161.13 MHz
1
STS-192, 0 bytes
0% increase
9.953 Gbps
622.08 MHz
STS-192, Reed Soloman - 255/238
7.14% increase
10.664 Gbps
666.514 MHz
STS-192, Reed Soloman - 255/237
7.59% increase
10.709 Gbps
669.31 MHz
10 Gigabit Ethernet
0% increase
10.000 Gbps
625.00 MHz
10 Gigabit Ethernet 64/66B Encoded
3.125% increase
10.3125 Gbps
644.52 MHz
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