參數(shù)資料
型號(hào)： S19237PB13
廠商： APPLIEDMICRO INC
元件分類： 數(shù)字傳輸電路
英文描述： TRANSCEIVER, PBGA255
封裝： PLASTIC, BGA-255
文件頁(yè)數(shù)： 24/60頁(yè)
文件大?。?/td> 1418K
代理商： S19237PB13
30
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
TXCAP1
TXCAP2
Analog
D5
D6
Transmit Loop Filter Capacitors. Connections for external loop filter
capacitors and resistors. See Figure 22, External Loop Filter Compo-
nents, and Table 33, Transmit and Receive External Loop Filter Com-
ponents.
XVCO
MDIO
I
External Voltage Controlled Oscillator Select. This active high
input selects CSU_IN as the reference clock for the CSU block. In
this mode, CSU block uses CSU_IN as the reference clock instead of
using CSU_REFCLK directly. This signal can be accessed through
the MDIO bus register (Default = 0).
REFSEL
MDIO
I
Reference Select. Selects the reference clock frequency of the
transmit reference clock (CSU_REFCLK). See Table 1, Reference
can be accessed through the MDIO bus register (Default = 1).
PHINIT
MDIO
I
Phase Initialization. Asynchronous input that initializes the PHINIT.
See Figure 23, FIFO Initialization. This signal can be accessed
through the MDIO bus register (Default = 0).
AUTO_FIFO_INIT
MDIO
I
FIFO Initialization. This active high control input internally connects
the transmit FIFO signals (PHERR and PHINIT) and automatically
initializes the FIFO in case of a PCLK/PICLK set-up or hold time vio-
lation. This input can be accessed through the MDIO bus register
(Default = 1).
TX_BIST_EN
MDIO
I
Transmit Built-In Self Test Enable. This active high input enables
the transmit built-in self test mode. In this mode the PRBS generator
will start sending the pattern through the parallel inputs and transmit
checker will be activated. This signal can be accessed through the
MDIO bus register (Default = 0).
TX_BIST_CLR
MDIO
I
Transmit Built-In Self Test Clear. This active high level sensitive
input clears the transmit built-in self test error. The TX_BIST_ERR
flag can be cleared by asserting TX_BIST_CLR high in the BIST
mode or by resetting (RSTB) the S19237. This signal can be
accessed through the MDIO bus register (Default = 0).
CSU_INP
CSU_INN
REFCLK
Diff CML
I
B4
A4
Clock Synthesizer Input. Input to the internal CSU. Used to gener-
ate the serial transmit data. This input is internally biased and termi-
nated. This input must be AC coupled.
TXPD
MDIO
I
Transmitter Power Down. This active high control input powers
down the CSU and transmitter path. This signal can be accessed
through the MDIO bus register (Default = 0).
RECEIVER INPUTS
SERDATIP
SERDATIN
High
Speed
Diff CML
I
L1
N1
Serial Data Input. Differential high-frequency serial data input to lim-
iting post-amp for small signal gain. Internally biased and terminated
100
line-to-line (50 + 50 with center tap capacitor). This input
must be AC coupled.
CENTER_TAP
Analog
I
J1
Center Tap Input. This input should be connected to a broadband
0.01
F capacitor to ground.
Table 17. Input Pin Assignments and Descriptions (Continued)
Pin Name
Level
I/O
Pin#
Description
相關(guān)PDF資料
PDF描述
S1950E-FREQ-OUT25 CRYSTAL OSCILLATOR, CLOCK, 80 MHz - 125 MHz, ACMOS OUTPUT
S1F78100Y2A0 6 V FIXED POSITIVE REGULATOR, PSSO3
S1F78100Y2B0 5 V FIXED POSITIVE REGULATOR, PSSO3
S1F78100Y2C0 3.2 V FIXED POSITIVE REGULATOR, PSSO3
S1F78100Y2F0 2.2 V FIXED POSITIVE REGULATOR, PSSO3
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S19237PB13-2 制造商:AppliedMicro 功能描述:
S19237PBICC 制造商:AppliedMicro 功能描述:IC INTERFACE TRANSCEIVER LOW POWER CMOS 255 BGA 制造商:AMCC 功能描述:
S19238CBI 制造商:AppliedMicro 功能描述:
S19250 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC
S19250PBIC 制造商:AppliedMicro 功能描述:10G SERDES EDC/SFI-4
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*