參數(shù)資料
型號(hào)： S19237PB13
廠(chǎng)商： APPLIEDMICRO INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： TRANSCEIVER, PBGA255
封裝： PLASTIC, BGA-255
文件頁(yè)數(shù)： 27/60頁(yè)
文件大小： 1418K
代理商： S19237PB13
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
AMCC Confidential and Proprietary
DS1454
33
Data Sheet
RLPTIME
MDIO
I
Reference Loop Timing. This active high input selects Reference
Loop Timing Mode. In this mode, the transmitter CSU utilizes the
receiver POCLK instead of the CSU_REFCLK. See Table 10 for
details. This signal can be accessed through the MDIO bus register
(Default = 0).
BIST_PTRN[15:0]
MDIO
I
User Defined BIST Pattern (BIST_PTRN[15:0]). This user defined
pattern is output from the transmit or the receive pattern generator.
This pattern is loaded on the rising edge of TX_BIST_EN or
RX_BIST_EN. The user defined pattern can be selected by proper
setting of the PRBS_SEL[1:0]. This input can be accessed through
the MDIO bus register.
PRBS_SELECT[1:0]
MDIO
I
Pattern Select (PRBS_SELECT[1:0]). The pattern select bits select
between the different PRBS patterns and the user defined pattern.
See Table 11 for details. This input can be accessed through the
MDIO bus register (Default = 0,0).
BER_SELECT[1:0]
MDIO
I
Bit Error Rate Range Select (BER_SELECT[1:0]). The bit error
rate range select bits selects the appropriate bit error rate range for
reporting the but error rate. See Table 12 for details. This input can
be accessed through the MDIO bus register (Default = 0,0).
BER_RSTB
MDIO
I
Bit Error Rate Reset (BER_RSTB). This input selects whether the
BER_OUT[9:0] is reset after each terminal count. Active high. When
active, BER_OUT[9:0] is not reset after each terminal count, but
instead continues to accrue errors. This input can be accessed
through the MDIO bus register (Default = 0).
MDIO
LVCMOS
Pull Up
I/O
M14
Management Data Control Input/Output Bus. Bi-directional 2-wire
bus for efficient inter-IC control. This bus reads from and writes into
most of the S19237 control logic.
MDC
LVCMOS
I
L12
Management Clock Control Input. Clock for Bi-directional MDIO
bus.
ADDRESS4
ADDRESS3
ADDRESS2
ADDRESS1
ADDRESS0
LVCMOS
Pull
Down
I
K12
J13
F13
F12
E12
Reserved address Lines. These address bits are used to uniquely
identify each S19237 device if multiple S19237 devices are con-
trolled by a single microprocessor. The ADDRESS[4:0] lines can be
pulled up by directly connecting to
VDD_1.8 V.
Table 18. Output Pin Assignments and Descriptions
Pin Name
Level
I/O
Pin#
Description
TRANSMITTER OUTPUTS
TSDP
TSDN
High
Speed
diff CML
O
D1
F1
Transmit Serial Data. Serial data stream signals, normally con-
nected to an optical transmitter module. Output return loss, S22 of
-12dB at 15 GHz.
PCLKP
PCLKN
LVDS
O
D8
C8
Parallel Clock. A 622.08 MHz (or equivalent FEC/10 Gigabit Ether-
net rate) reference clock. It is normally used to coordinate data
transfers between upstream logic and the S19237 device.
Table 17. Input Pin Assignments and Descriptions (Continued)
Pin Name
Level
I/O
Pin#
Description
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