參數(shù)資料
型號: S19237PB13
廠商: APPLIEDMICRO INC
元件分類: 數(shù)字傳輸電路
英文描述: TRANSCEIVER, PBGA255
封裝: PLASTIC, BGA-255
文件頁數(shù): 28/60頁
文件大?。?/td> 1418K
代理商: S19237PB13
34
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
TX_155MCKP
TX_155MCKN
LVDS
O
B8
A8
155.52 MHz Clock Output. 155.52 MHz (or equivalent FEC/10
Gigabit Ethernet rate) clock output from CSU_REFCLK. The output
can be connected to the reference clock input (CRU_REFCLKP/N)
of the clock recovery function (such as that of the S19237).
TX_LOCKDET
LVCMOS
& MDIO
Pull Up
O
J14
Transmit Lock Detect. Active high. Goes active after the PLL has
locked
to
the
clock
provided
on
the
CSU_REFCLK
pins.
TX_LOCKDET is an asynchronous output.
PHERR
MDIO
O
Phase Error. Pulses high during each PCLK cycle for which there is
a potential FIFO overrun/underrun condition. No additional external
components required. Should be directly connected to PHINIT on
the MDIO bus.
TX_ALARM
MDIO
O
Transmit Alarm Output. This output is an electrical “OR” of all the
transmit alarms [(“NOT” TX_LOCKDET) “OR” (PHERR)].
PD_UPP
PD_UPN
PD_DWNP
PD_DWNN
Phase
Detector
Diff CML
O
A6
A5
B5
B6
Phase Detector Output. This output is used to drive an external
charge pump which, in turn, drives the external VCO. The external
VCO output is then fed into the CSU_INP/N input to be used as the
transmit reference clock for the CSU block.
TX_BIST_ERR
MDIO
O
Transmit Built-In Self Test Error. This output indicates a bit error
in the transmit built-in self test loop.
RECEIVER OUTPUTS
POCLKP
POCLKN
LVDS
O
L14
K14
Parallel Output Clock. Regenerated 622.08 MHz (or equivalent
FEC/10 Gigabit Ethernet rate) differential output clock, synchro-
nized to the parallel output data. See Figure 21, Receiver Timing
Table 18. Output Pin Assignments and Descriptions (Continued)
Pin Name
Level
I/O
Pin#
Description
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