參數(shù)資料
型號(hào)： S19237PB13
廠商： APPLIEDMICRO INC
元件分類： 數(shù)字傳輸電路
英文描述： TRANSCEIVER, PBGA255
封裝： PLASTIC, BGA-255
文件頁數(shù)： 26/60頁
文件大小： 1418K
代理商： S19237PB13
32
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
KILLMCKCLKB
MDIO
I
Kill RX_622MCK Clock Output. Active low. For normal operation,
KILLMCKCLKB is high. When this input is low, it will force the
RX_622MCK output to a logic ‘0’ state. This signal can be accessed
through the MDIO bus register (Default = 1).
KILLPOCLKB
MDIO
I
Kill POCLK Output. Active low. For normal operation, KILLPOCLKB
is high. When this input is low, it will force the POCLK output to a
logic ‘0’ state. This signal can be accessed through the MDIO bus
register (Default = 1).
RX_BIST_EN
MDIO
I
Receive Built-In Self Test Enable. This active high input enables
the receive built-in self test mode. In this mode the PRBS generator
will start sending the pattern through the parallel data output and
receive checker will be activated. This signal can be accessed
through the MDIO bus register (Default = 0).
RX_BIST_CLR
MDIO
I
Receive Built-In Self Test Clear. This active high level sensitive
input clears the receive built-in self test error. The RX_BIST_ERR
flag can be cleared by asserting RX_BIST_CLR high in the BIST
mode or by resetting (RSTB) the S19237. This signal can be
accessed through the MDIO bus register (Default = 0).
RXPD
MDIO
I
Receiver Power Down. This active high control input powers down
the CRU and receiver path. This signal can be accessed through the
MDIO bus register (Default = 0).
COMMON INPUTS
RSTB
LVCMOS
Pull Up
I
G13
Master Reset. Reset input for the S19237. Must remain low for 100
ns to accurately reset the transmitter. During reset, PCLK does not
toggle. For normal operation, connect to
VDD_1.8 V. For normal sys-
tem power sequencing on power-up, no reset is required. This signal
can be accessed through an external pin (Default = 1).
DATA_SWAP
MDIO
I
Parallel Input and Output Data Bus Reversal. Reverses the order
of the parallel input and output data bus (PINP/N[15:0] and POUTP/
N[15:0]). DATA_SWAP input should be programmed to logic low
when S19237 is used with 300-pin MSA connector. DATA_SWAP
input should be programmed to logic high when S19237 is used with
200-pin MSA connector. This signal can be accessed through the
MDIO bus register (Default = 1).
DLEB
MDIO
I
Diagnostic Loopback Enable. This active low input selects the
Diagnostic Loopback Timing Mode. In this mode, the transmitter out-
going serial data is re-routed to the receiver. This signal can be
accessed through MDIO bus register (Default = 1).
LLEB
MDIO
I
Line Loopback Enable. This active low input selects the Line Loop-
back Timing Mode. In this mode, the receiver parallel data is routed
to the transmitter and re-transmitted back to the source. See Table 9
for details. This signal can be accessed through the MDIO bus regis-
ter (Default = 1).
SLPTIME
MDIO
I
Serial Loop Timing. This active high input selects the Serial Loop
Timing Mode. In this mode, the transmitter parallel-to-serial converter
will utilize the internal RSCLK from the receiver rather than the CSU
clock. See Table 10 for details. This signal can be accessed through
the MDIO bus register (Default = 0).
Table 17. Input Pin Assignments and Descriptions (Continued)
Pin Name
Level
I/O
Pin#
Description
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