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參數(shù)資料
| 型號： | S19237PB13 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封裝： | PLASTIC, BGA-255 |
| 文件頁數(shù)： | 11/60頁 |
| 文件大小： | 1418K |
| 代理商： | S19237PB13 |
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S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
AMCC Confidential and Proprietary
DS1454
19
Data Sheet
AMCC recommends that DATA_SWAP input be pro-
grammed to logic low when S19237 is used with the
300-pin MSA connector. The S19237 should be
placed on the top side of the module when used with
the 300-pin MSA connector. See Table 17 for details.
This input is only accessible through the MDIO bus
register.
COMMON OUTPUT PIN DESCRIPTION
Transmit and Receive Alarm (TX_RX_ALARM) –
MDIO Register and External Pin
The active high LVCMOS transmit and receive alarm
(TX_RX_ALARM) signal indicates an active alarm on
the transmit or the receive output. This output is an
electrical “OR” of all the transmit and receive alarms
[TX_ALARM “OR” (“NOT” RX_LOCKDET)]. This out-
put can be accessed through the MDIO bus register
and through an external LVCMOS pin.
Built In Self Test Active (BIST_ACTIVE) –
MDIO Register
This output indicates that the BIST checker is active
and is progressively checking data. This signal moni-
tors the RX checker when the RX_BIST_EN is active
and TX checker when TX_BIST_EN is active. This
output is only accessible through the MDIO bus
register.
Bit Error Rate Count (BER_COUNT[9:0]) – MDIO
Register
This output holds the bit error rate being received by
the checker with the exponent being determined by
the BER_SELECT[1:0] input. This signal monitors the
RX checker count when the RX_BIST_EN is active
and TX checker count when TX_BIST_EN is active.
This output is only accessible through the MDIO bus
register.
Bit Error Rate Overflow (BER_OVERFLOW) – MDIO
Register
This output indicates that the BER_COUNT[9:0] has
o v er f l owe d an d bit er r o r r a t e r a n g e se lect
(BER_SELECT[1:0]) needs to be changed. This signal
is active high and is latched high. This signal monitors
the RX checker count when the RX_BIST_EN is active
and TX checker count when TX_BIST_EN is active.
This output is only accessible through the MDIO bus
register.
Terminal Count Monitor (TERM_COUNT) – MDIO
Register
This output monitors for the terminal count of the
PRBS checker. The terminal count is set by the
BER_SELECT[1:0] register. See Table 12 for details.
Each transition of this signal indicates that the terminal
count has been reached. This signal is initially set low
upon RSTB or when TX_BIST_EN/RX_BIST_EN are
activated. The TERM_COUNT makes a low to high
transition when the first terminal count is reached. A
transition on TERM_CO UNT will s e t the
BER_COUNT[9:0] register to zero depending upon the
BER_RSTB setting. When BER_RSTB is active
(high), BER_OUT[9:0] is not reset after each terminal
count, but instead continues to accrue errors. This out-
put is only accessible through the MDIO bus register.
TRANSMITTER FUNCTIONAL
DESCRIPTION
MUX Operation
The S19237 performs the serializing stage in the pro-
cessing of a transmit SONET STS-192/10 Gigabit
Ethernet bit serial data stream. It converts the 16-bit
pa ra llel da ta s t re am to bit se ria l for m a t fr om
9.953 Gbps to 10.709 Gbps. The rate will depend
upon the CSU_REFCLK frequency used. A high-fre-
quency bit clock is generated from a 155.52 or
622.08 MHz (or equivalent FEC/10 Gigabit Ethernet
rate) frequency reference by using a clock synthesizer
consisting of an on-chip phase-lock loop circuit with a
divider, VCO and loop filter.
Clock Synthesizer
The clock synthesizer shown in the block diagram in
Figure 5, is a monolithic PLL that generates the serial
output clock frequency locked to the input Reference
Clock (CSU_REFCLKP/N).
The CSU_REFCLKP/N input must be generated from
a crystal oscillator which has a frequency accuracy
that meets the value stated in Table 22 in order for the
Transmit Serial Data (TSDP/N) frequency to have the
accuracy required for operation in a SONET/10 Giga-
bit Ethernet system. The CSU_REFCLK must also
mee t t he pha se n o ise r equir e men ts sh own in
Figures 18 and 19 in order to meet the jitter generation
specifications as defined in GR-253-CORE. Lower
accuracy crystal oscillators may be used in applica-
tions less demanding than the SONET/SDH.
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