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參數(shù)資料
| 型號： | S19237PB13 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封裝： | PLASTIC, BGA-255 |
| 文件頁數(shù)： | 25/60頁 |
| 文件大?。?/td> | 1418K |
| 代理商： | S19237PB13 |
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S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
AMCC Confidential and Proprietary
DS1454
31
Data Sheet
PAOFFADJ9
PAOFFADJ8
PAOFFADJ7
PAOFFADJ6
PAOFFADJ5
PAOFFADJ4
PAOFFADJ3
PAOFFADJ2
PAOFFADJ1
PAOFFADJ0
MDIO
I
Post-Amp Offset Adjust. Used to correct duty cycle distortion on
the input data signal. See Table 6 for details. This signal can be
accessed through the MDIO bus register. The default state will
depend up on the fuse settings and may vary from one device to
another.
ADAPOFFADJ
MDIO
I
Adaptive Post-Amp Offset Adjust Enable. Enables the adaptive
offset adjustment control. See Table 7 for details. This signal can be
accessed through the MDIO bus register (Default = 1).
PAEQUADJ2
PAEQUADJ1
PAEQUADJ0
MDIO
I
Post-Amp Equalization Adjust (ISI Compensation Control). Used
to adjust input serial data equalization control. This signal compen-
sates for the ISI. See Table 8 for details. This signal can be accessed
through the MDIO bus register (Default = 0,0,0).
PHASE_ADJ2
PHASE_ADJ1
PHASE_ADJ0
MDIO
I
Phase Adjust. Used to adjust the phase between the recovered
clock and data. The phase adjust can improve the bit error rate and
link budget. See Table 5 for details. This signal can be accessed
through the MDIO bus register (Default = 0,0,0).
CRU_REFCLKP
CRU_REFCLKN
REFCLK
Diff CML
I
T4
T3
Receive Reference Clock. 155.52 MHz (or equivalent FEC/10
Gigabit Ethernet frequency) input used as the reference for the inter-
nal bit clock frequency synthesizer. This input is internally biased and
terminated. This input must be AC coupled.
RXCAP1
RXCAP2
Analog
P6
P7
Receive Loop Filter Capacitors. Connections for external loop filter
capacitors and resistors. See Figure 22, External Loop Filter Compo-
Components.
LCKREFN
MDIO
I
Lock to Reference. Active low. When active, the PLL is forced to
lock to the local reference clock input (CRU_REFCLK). If unused,
connect to logic ‘1’ for normal operation. This signal can be accessed
through MDIO bus register (Default = 1).
SDLVCMOS
LVCMOS
Pull Up
I
M7
Signal Detect. An LVCMOS single-ended input to be driven by the
external optical receiver module to indicate a loss of received optical
power. When a loss-of-light condition occurs, the internal PLL will be
forced to lock to the CRU_REFCLK input signal. The POUTP/N will
be forced to a logic ‘0’ state when SDLVCMOS is inactive. The active
level of this input may be programmed by SD_POL.
SD_POL
MDIO
I
Signal Detect Polarity. This signal will set the SDLVCMOS input as
either active high or active low. Setting this pin low will set the
SDLVCMOS input as active low. Setting this pin high will set the
SDLVCMOS input as active high. This signal can be accessed
through the MDIO bus register (Default = 1).
KILLPOUTB
MDIO
I
Kill Parallel Data Output. Active low. For normal operation,
KILLPOUTB is high. When this input is low, it will force the
POUT[15:0] output to a logic ‘0’ state. This signal can be accessed
through the MDIO bus register (Default = 1).
Table 17. Input Pin Assignments and Descriptions (Continued)
Pin Name
Level
I/O
Pin#
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S19237PB13-2 | 制造商:AppliedMicro 功能描述: |
| S19237PBICC | 制造商:AppliedMicro 功能描述:IC INTERFACE TRANSCEIVER LOW POWER CMOS 255 BGA 制造商:AMCC 功能描述: |
| S19238CBI | 制造商:AppliedMicro 功能描述: |
| S19250 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC |
| S19250PBIC | 制造商:AppliedMicro 功能描述:10G SERDES EDC/SFI-4 |
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