![](http://datasheet.mmic.net.cn/260000/PTM1300FBEA_datasheet_15959396/PTM1300FBEA_473.png)
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-187
Unsigned 16-bit load
pseudo-op for uld16d(0)
SYNTAX
[ IF rguard ] uld16 rsrc1
→
rdest
FUNCTION
if
rguard
then {
if
PCSW.bytesex = LITTLE_ENDIAN
then
bs
←
1
else
bs
←
0
temp<7:0>
←
mem[rsrc1+ (1
⊕
bs)]
temp<15:8>
←
mem[rsrc1+ (0
⊕
bs)]
rdest
←
zero_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dmem
197
1
No
—
3
4, 5
DESCRIPTION
The
uld16
operation is a pseudo operation transformed by the scheduler into an
uld16d(0)
with the same
argument. (Note: pseudo operations cannot be used in assembly source files.)
The
uld16
operation loads the 16-bit memory value from the address contained in rsrc1 zero extends it to 32 bits,
and writes the result in rdest If the memory address contained in rsrc1 is not a multiple of 2, the result of
uld16
is
undefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending on
the current setting of the bytesex bit in the PCSW.
The result of an access by
uld16
to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32-bit loads and stores.
The
uld16
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguardis 1, rdestis written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
uld16
has no side effects whatever.
EXAMPLES
Initial Values
Operation
Result
r10 = 0xd00, [0xd00] = 0x22,
[0xd01] = 0x11
r30 = 0, r20 = 0xd04, [0xd04] = 0x84,
[0xd05] = 0x33
r40 = 1, r20 = 0xd04, [0xd04] = 0x84,
[0xd05] = 0x33
r50 = 0xd01
uld16 r10
→
r60
r60
←
0x00002211
IF r30 uld16 r20
→
r70
no change, since guard is false
IF r40 uld16 r20
→
r80
r80
←
0x00008433
uld16 r50
→
r90
r90 undefined (0xd01 is not a multiple of 2)
SEE ALSO
uld16d ild16 ild16d uld16r
ild16r uld16x ild16x
uld16