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PRODUCT SPECIFICATION
15-1
Variable Length Decoder
Chapter 15
by Gene Pinkston and Selliah Rathnam
15.1
VLD OVERVIEW
The variable length decoder (VLD) unit Huffman-de-
codes MPEG-1 and MPEG-2 (Main Profile) video bit-
streams[1-3]. This chapter describes a programmers
view of the VLD.
The VLD reads an MPEG stream from SDRAM, decodes
the bitstream under the control of DSPCPU and outputs
two data streams. The output data streams contain mac-
roblock header information and the run-length encoded
DCT coefficients. The output data streams are stored in
the SDRAM buffers.
The VLD unit, operates independently during the slice
decoding process. The remaining decoding of the MPEG
stream is carried out by the DSPCPU.
15.2
VLD OPERATION
Enabled by the DSPCPU, the VLD unit can be initialized
by hardware or software reset operations. Hardware re-
set is provided by the external TRI_RESET# pin. Soft-
ware reset is provided by one of the VLD commands.
The DSPCPU controls the VLD through the VLD com-
mand register. There are five commands supported by
the VLD:
Shift the bitstream by some number of bits (a maxi-
mum of 15-bit shift)
Search for the next start code
Reset the VLD
Parse some number of macroblocks
Flush VLD output buffers to SDRAM
The normal mode of operation will be for the DSPCPU to
request that the VLD to parse some number of macrob-
locks. Once the VLD has begun parsing macroblocks, it
may stop for any one of the following reasons:
The command was completed with no exceptions
A start code was detected
An error was encountered in the bitstream
HWY_BUS
RD Buffer
64 Bytes
Macroblock
Hdr WR FIFO
DMA
ENGINE
Control
status
status
MMIO &
CONF REGs
SHIFTER
start_code_
detector
mb_addr
mb_type
cbp
dmv &
motion
dct_lum
dct_chr
dctcoef
(0)
dctcoef
(1)
escape_codes
VLD
FLOW
Control
Interrupt
Run-Level
WR FIFO
Figure 15-1. VLD block diagram
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