![](http://datasheet.mmic.net.cn/260000/PTM1300FBEA_datasheet_15959396/PTM1300FBEA_323.png)
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-37
Floating-point absolute value
SYNTAX
[ IF rguard ] fabsval rsrc1
→
rdest
FUNCTION
if
rguard
then {
if
(float)rsrc1< 0
then
rdest
←
–(float)rsrc1
else
rdest
←
(float)rsrc1
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
falu
115
1
No
—
3
1, 4
DESCRIPTION
The
fabsval
operation computes the absolute value of the argument rsrc1 and stores the result into rdest All
values are in IEEE single-precision floating-point format. If an argument is denormalized, zero is substituted for the
argument before computing the absolute value, and the IFZ flag in the PCSW is set. If
fabsval
causes an IEEE
exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can
be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw
operation. The
update of the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute
operations update the PCSW at the same time, the net result in each exception flag is the logical OR of all
simultaneous updates ORed with the existing PCSW value for that exception flag.
The
fabsvalflags
operation computes the exception flags that would result from an individual
fabsval
.
The
fabsval
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdestis not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x40400000 (3.0)
r35 = 0xbf800000 (-1.0)
r40 = 0x00400000 (5.877471754e-39)
r45 = 0xffffffff (QNaN)
r50 = 0xffbfffff (SNaN)
r10 = 0,
r55 = 0xff7fffff (–3.402823466e+38)
r20 = 1,
r55 = 0xff7fffff (–3.402823466e+38)
fabsval r30
→
r90
fabsval r35
→
r95
fabsval r40
→
r100
fabsval r45
→
r105
fabsval r50
→
r110
IF r10 fabsval r55
→
r115
r90
←
0x40400000 (3.0)
r95
←
0x3f800000 (1.0)
r100
←
0x0 (+0.0), IFZ set
r105
←
0xffffffff (QNaN)
r110
←
0xffffffff (QNaN), INV set
no change, since guard is false
IF r20 fabsval r55
→
r120
r120
←
0x7f7fffff (3.402823466e+38)
SEE ALSO
iabs dspiabs dspidualabs
fabsvalflags readpcsw
writepcsw
fabsval