![](http://datasheet.mmic.net.cn/260000/PTM1300FBEA_datasheet_15959396/PTM1300FBEA_447.png)
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-161
16-bit store
pseudo-op for h_st16d(0)
SYNTAX
[ IF rguard ] st16 rsrc1 rsrc2
FUNCTION
if
rguard
then {
if
PCSW.bytesex = LITTLE_ENDIAN
then
bs
←
1
else
bs
←
0
mem[rsrc1+ (1
⊕
bs)]
←
rsrc2<7:0>
mem[rsrc1+ (0
⊕
bs)]
←
rsrc2<15:8>
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dmem
30
2
No
—
n/a
4, 5
DESCRIPTION
The
st16
operation is a pseudo operation transformed by the scheduler into an
h_st16d(0)
with the same
arguments. (Note: pseudo operations cannot be used in assembly files.)
The
st16
operation stores the least-significant 16-bit halfword of rsrc2 into the memory locations pointed to by the
address in rsrc1 This store operation is performed as little-endian or big-endian depending on the current setting of
the bytesex bit in the PCSW.
If
st16
is misaligned (the memory address in rsrc1 is not a multiple of 2), the result of
st16
is undefined, and the
MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE (TRaP on
Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next interruptible jump.
The result of an access by
st16
to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32-bit loads and stores.
The
st16
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st16 has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
Initial Values
Operation
Result
r10 = 0xd00, r80 = 0x44332211
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd
r60 = 1, r30 = 0xd02,
r70 = 0xaabbccdd
st16 r10 r80
IF r50 st16 r20 r70
[0xd00]
←
0x22, [0xd01]
←
0x11
no change, since guard is false
IF r60 st16 r30 r70
[0xd02]
←
0xcc, [0xd03]
←
0xdd
SEE ALSO
st16d h_st16d st8 st8d
st32 st32d
st16