![](http://datasheet.mmic.net.cn/260000/PTM1300FBEA_datasheet_15959396/PTM1300FBEA_173.png)
Philips Semiconductors
PCI Interface
PRODUCT SPECIFICATION
11-17
Figure 11-13
illustrates back-to-back DMA burst data
transfers. The ICP is capable of exploiting the high band-
width available with back-to-back DMA operations when
it is writing image data to a frame buffer on a PCI video
card.
The timing of
Figure 11-13
assumes that the PCI bus is
granted to TM1300 until at least the beginning of the sec-
ond DMA burst operation. For as long as bus ownership
is granted to TM1300 and the ICP has queued requests
for data transfer, the PCI interface will perform back-to-
back DMA operations. If the target eventually becomes
unable to accept more data, it signals a disconnect on
the TM1300 PCI interface. The PCI interface remembers
where the DMA burst was interrupted and attempts to re-
start from that point after two bus clocks.
11.9
LIMITATIONS
11.9.1
Bus Locking
The PCI interface does not implement lock#, sbo, and
sbone pins. Consequently, it is possible for both the
DSPCPU and external PCI initiators to write to a critical
memory section simultaneously. Software must imple-
ment policies to guarantee memory coherency.
11.9.2
No Expansion ROM
TM1300 does not implement the PCI expansion ROM
capability.
11.9.3
No Cacheline Wrap Address
Sequence
The PCI interface does not implement the PCI cacheline-
wrap address mode for external PCI initiators that ac-
cess TM1300 SDRAM.
11.9.4
No Burst for I/O or Configuration
Space
Only single-data-phase transactions to configuration and
I/O spaces are supported. The byte-enable signals se-
lect the byte(s) within the addressed word.
11.9.5
Word-Only MMIO Register Access
External initiators can access TM1300 MMIO registers
only as full words. The byte-enable signals have no ef-
fect on the data transferred. External initiators must read
and write all four bytes of MMIO registers.
pci_clk
frame#
ad
c/be#
irdy#
trdy#
devsel#
1
2
3
18
19
20
Address
Byte Enables
35
Byte Enables
Command
Data 1
Data 15
Data 16
Data 17
Data 31
Data 32
36
D
D
D
D
D
D
Figure 11-13. Back-to-back PCI burst write operations with 16 data phases which might be generated by the
ICP when writing image data to a PCI-resident video frame buffer.