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Philips Semiconductors
Enhanced Video Out
PRODUCT SPECIFICATION
7-25
2. Choose a value for PLL_S and PLL_T. For 8-40 MHz
operation, a value of 1 (which selects division by 2) is
recommended.
3. Choose a value for CLOCK_SELECT. For 8-81 MHz
operation, CLOCK_SELECT = 00 is recommended.
4. Assign values to the VO_CTL register containing the
above choices. The first assignment with
CLOCK_SELECT not equal to 0x3 enables the PLL
system. Allow for a maximum of 50 microseconds to
achieve lock.
Once the PLL is locked, small changes to the DDS fre-
quency are allowed, and the VO_CLK output will
smoothly track the frequency change.
Note: Most consumer electronics equipment imposes
very high precision requirements on the value of the col-
or burst frequency. A video encoder will derive the color
burst frequency from VO_CLK. When changing the
VO_CLK frequency in software to phase-lock the EVO to
a master reference, special care is required to keep the
color burst signal frequency within a tolerance of about
50 ppm. When using a Philips DENC (Digital Encoder),
the color burst frequency is derived from the master
DENC frequency by a programmable synthesizer on the
DENC chip. In this case, VO_CLK changes larger than
50 ppm are allowed by changing the DENC synthesizer
over its I
2
C interface to compensate for the VO_CLK
change.
Table 7-11
illustrates recommended settings.
Table 7-11. DDS and PLL example settings
Desired
Frequency
DDS frequency
PLL_S
PLL_T
CLOCK_SELECT
Usage
4 – 10 MHz
8 – 45 MHz
40 – 81 MHz
8 – 20 MHz
8 – 45 MHz
20 – 40.5 MHz
1 (divide by 2)
1 (divide by 2)
1 (divide by 2)
1 (divide by 2)
1 (divide by 2)
3 (divide by 4)
01 (T divider)
00 (VCO)
00 (VCO)
Custom low speed video
Standard or 16:9 digital video
High pixel rate custom video