![](http://datasheet.mmic.net.cn/260000/PTM1300FBEA_datasheet_15959396/PTM1300FBEA_343.png)
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-57
Sign of floating-point value
SYNTAX
[ IF rguard ] fsign rsrc1
→
rdest
FUNCTION
if
rguard
then {
if
(float)rsrc1= 0.0
then
rdest
←
0
else if
(float)rsrc1< 0.0
then
rdest
←
0xffffffff
else
rdest
←
1
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
fcomp
152
1
No
—
1
3
DESCRIPTION
The
fsign
operation sets the destination register, rdest to either 0, 1, or –1 depending on the sign of the argument
in rsrc1 rdest is set to 0 if rsrc1 is equal to zero, to 1 if rsrc1 is positive, or to –1 if rsrc1 is negative. The argument is
treated as an IEEE single-precision floating-point value; the result is an integer. If the argument is denormalized, zero
is substituted before computing the comparison, and the IFZ flag in the PCSW is set; thus, the result of
fsign
for a
denormalized argument is 0. If
fsign
causes an IEEE exception, the corresponding exception flags in the PCSW are
set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-point operation but can
only be reset by an explicit
writepcsw
operation. The update of the PCSW exception flags occurs at the same time
as rdest is written. If any other floating-point compute operations update the PCSW at the same time, the net result in
each exception flag is the logical OR of all simultaneous updates ORed with the existing PCSW value for that
exception flag.
The
fsignflags
operation computes the exception flags that would result from an individual
fsign
.
The
fsign
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdestis not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x40400000 (3.0)
r40 = 0xbf800000 (-1.0)
r50 = 0x80800000 (-1.175494351e-38)
fsign r50
→
r110
r60 = 0x80400000 (-5.877471754e-39)
fsign r60
→
r115
r10 = 0, r70 = 0xffffffff (QNaN)
r20 = 1, r70 = 0xffffffff (QNaN)
r80 = 0xff800000 (-INF)
fsign r30
→
r100
fsign r40
→
r105
r100
←
1
r105
←
0xffffffff (-1)
r110
←
0xffffffff (-1)
r115
←
0, IFZ flag set
no change, since guard is false
r117
←
0, INV flag set
r120
←
0xffffffff (-1)
IF r10 fsign r70
→
r116
IF r20 fsign r70
→
r117
fsign r80
→
r120
SEE ALSO
fsignflags readpcsw
writepcsw
fsign