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參數(shù)資料
| 型號： | PTM1300AEBEA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Programmable Media Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA292 |
| 封裝： | PLASTIC, SOT-553-1, BGA-292 |
| 文件頁數(shù)： | 211/533頁 |
| 文件大?。?/td> | 6857K |
| 代理商： | PTM1300AEBEA |
Philips Semiconductors
Image Coprocessor
PRODUCT SPECIFICATION
14-13
14.5.8
Implementation Overview: Vertical
Scaling and Filtering
Figure 14-14
shows a data flow block diagram of the ICP
vertical scaling algorithm implementation. Blocks of pix-
els are loaded sequentially into five input block buffers,
one for each of the 5 terms of the 5-tap filter. Each block
of pixels is transferred sequentially to the 5-tap filter. The
filter does scaling and filtering of the data and puts the re-
sulting pixels in the output buffer. Completed pixels in the
output buffer are written back to SDRAM.
In vertical scaling, five separate blocks of pixels, one for
each line, are required because the pixels are stored in
horizontal sequence in the SDRAM. The Y Counter steps
through the 64 horizontal pixels of the five input blocks
and writes the resulting pixels into the output block. Four
of the five blocks are used on the next pass, so that one
block of pixels in generates one block of pixels out ex-
cept for end conditions. The image is processed in 64-
pixel columns. Since the image to be filtered will not gen-
erally start or end on a block boundary, the number of
horizontal pixels for the first and last columns will be less
than 64 in these cases. Also, the data in the columns
must be aligned vertically. This results in the requirement
that the line-to-line address offset value must be a multi-
ple of 64 bytes. Note that only the address offset value is
modulo 64; the image to be filtered can start and stop
anywhere. Block alignment is not required.
Vertical scaling and filtering processes five 64-pixel input
line segments to generate one 64-pixel output segment.
When input lines Y
n-2
to Y
n+2
have been processed to
generate one 64-pixel output segment for output line Y
n
,
five new input segments are needed for the next output
line segment in the 64-pixel column, Y
n+1
. If the vertical
scale factor is 1.0 (no scaling), line segments Y
n-1
to
Y
n+2
are reused, a new block for Y
n+3
is loaded and the
block for line Y
n-2
is discarded.
To load Y
n+3
, the MCU adds the Y offset value to the
block address (upper 26 bits) of the Y Counter, and the
Y Counter selects the next Y block to be read from
SDRAM. The Y Counter points to the line block address
for last Y block loaded, and the Y offset value is the ad-
dress difference between the start of one line and the
start of the next, X0Y0 to X0Y1. The line offset is always
an integral number of SDRAM blocks. The line offset val-
ue must be added to the current line address to get the
next line address.
Up and down scaling use the U Counter and U Increment
value. The U Counter is used to detect how many lines
must be read (0 to 5) to generate the next output line and
to generate the vertical offset fraction for the 5-tap filter
for output lines that fall between the input lines. The U
Counter is set to its starting value (typically ‘0’) at the
start of the column, and the U Increment value is added
to the U Counter for each output line segment generated
in the column. For a scaling factor of 1.0, the U Increment
value is 1.0, and each line processed will generate a re-
quest for one block. If the scaling factor is 1/2, the incre-
ment value will be two, corresponding to moving down
two lines. In this case, twice the line offset is added to the
Y Counter value.
For up scaling by a factor of 2.0, the Y increment value is
0.5. This means two output lines are generated for each
input line. The U Counter increments as 0.0, 0.5, 1.0, 1.5,
2.0, etc. The LSBs of the U Counter (i.e. the fractional
part less than 1) are passed along to the filter to generate
the intermediate values. An LSB value of 0.5 means that
Input Pixels: Y
Output Pixels: Y’
1
2
3
4
5
6
Y’=F(Y3,Y2,Y1,Y2,Y3)
Y’=F(Y2,Y1Y2,Y3,Y4)
Y’=F(Y1,Y2,Y3,Y4,Y5)
Y’=F(Y2,Y3,Y4,Y5,Y6)
Y’=F(Y3,Y4,Y5,Y6,Y5)
2N: Y’=F(Y4,Y5,Y6,Y5,Y4)
(3)
(2)
(5) (4)
Mirrored Pixels
Figure 14-12. Horizontal Pixel Mirroring
SDRAM Bus
Filter Action
Read X0
Write Xa
Read X1
Filter X1 => Xb
Filter X0 => Xa
Read X2
Write Xb
Filter X2 => Xc
Read X3
Figure 14-13. SDRAM and horizontal filter block timing
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相關(guān)代理商/技術(shù)參數(shù) |
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| PTM1300EBEA | 制造商:NXP Semiconductors 功能描述: |
| PTM1300FBEA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable Media Processor |
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