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TM1300 Data Book
Philips Semiconductors
A-174
PRODUCT SPECIFICATION
Convert floating-point to unsigned integer using
PCSW rounding mode
SYNTAX
[ IF rguard ] ufixieee rsrc1
→
rdest
FUNCTION
if
rguard
then {
rdest
←
(unsigned long) ((float)rsrc1)
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
falu
123
1
No
—
3
1, 4
DESCRIPTION
The
ufixieee
operation converts the single-precision IEEE floating-point value in rsrc1to an unsigned integer and
writes the result into rdest Rounding is according to the IEEE rounding mode bits in PCSW. If rsrc1 is denormalized,
zero is substituted before conversion, and the IFZ flag in the PCSW is set. If
ufixieee
causes an IEEE exception,
such as overflow or underflow, the corresponding exception flags in the PCSW are set. The PCSW exception flags are
sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw
operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If any
other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the
logical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
The
ufixieeeflags
operation computes the exception flags that would result from an individual
ufixieee
.
The
ufixieee
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdestis not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x40400000 (3.0)
r35 = 0x40247ae1 (2.57)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38)
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38)
r45 = 0x7f800000 (+INF))
ufixieee r30
→
r100
ufixieee r35
→
r102
IF r10 ufixieee r40
→
r105
r100
←
3
r102
←
3, INX flag set
no change, since guard is false
IF r20 ufixieee r40
→
r110
r110
←
0x0, INV flag set
ufixieee r45
→
r112
ufixieee r50
→
r115
ufixieee r60
→
r117
ufixieee r70
→
r120
ufixieee r80
→
r122
r112
←
0xffffffff (2
32
-1), INV flag set
r115
←
0, INV flag set
r117
←
0, IFZ set
r120
←
0, INV flag set
r122
←
0, INV flag set
r50 = 0xbfc147ae (-1.51)
r60 = 0x00400000 (5.877471754e-39)
r70 = 0xffffffff (QNaN)
r80 = 0xffbfffff (SNaN)
SEE ALSO
ifixieee ifixrz ufixrz
ufixieee