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TM1300 Data Book
Philips Semiconductors
A-32
PRODUCT SPECIFICATION
Quad clipped add of unsigned/signed bytes
SYNTAX
[ IF rguard ] dspuquadaddui rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then {
for
(i
←
0, m
←
31, n
←
24; i < 4; i
←
i + 1, m
←
m – 8, n
←
n – 8)
{
temp
←
zero_ext8to32(rsrc1<m:n>) + sign_ext8to32(rsrc2<m:n>)
if
temp < 0
then
rdest<m:n>
←
0
else if
temp > 0xff
then
rdest<m:n>
←
0xff
else
rdest<m:n>
←
temp<7:0>
}
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dspalu
78
2
No
—
2
1, 3
DESCRIPTION
As shown below, the
dspuquadaddui
operation computes four separate sums of the four pairs of corresponding 8-
bit bytes of rsrc1 and rsrc2 The bytes in rsrc1 are considered unsigned values; the bytes in rsrc2 are considered
signed. The four sums are clipped into the unsigned range [255..0] (or [0xff..0]); thus, the final byte sums are
unsigned. All computations are performed without loss of precision.
The
dspuquadaddui
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls
the modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis not changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x02010001, r40 = 0xffffff01
r10 = 0, r60 = 0x9c9c6464, r70 = 0x649c649c
IF r10 dspuquadaddui r60 r70
→
r80
dspuquadaddui r30 r40
→
r50
r50
←
0x01000002
no change, since guard is
false
r90
←
0xff38c800
r20 = 1, r60 = 0x9c9c6464, r70 = 0x649c649c
IF r20 dspuquadaddui r60 r70
→
r90
0
1
3
rsrc1
0
1
3
rsrc2
0
3
rdest
+
+
+
+
2
7
2
7
7
1
2
0
9
0
9
0
9
0
9
Four full-precision
10-bit signed sums
Clip to [255..0]
unsigned
unsigned
unsigned
unsigned
signed
signed
signed
signed
signed
signed
signed
signed
unsigned
unsigned
unsigned
unsigned
Clip to [255..0]
Clip to [255..0]
Clip to [255..0]
SEE ALSO
dspidualadd
dspuquadaddui