![](http://datasheet.mmic.net.cn/260000/PTM1300FBEA_datasheet_15959396/PTM1300FBEA_433.png)
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-147
prefetch with index
SYNTAX
[ IF rguard ] prefr rsrc1 rsrc2
FUNCTION
i f
rguard
then {
cache_block_mask = ~(cache_block_size - 1)
data_cache <- mem[(rsrc1 + rscr2) & cache_block_mask]
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dmemspec
210
2
No
-
-
5
DESCRIPTION
The prefr operation loads the one full cache block size of memory value from the address computed by
((rsrc1+rscr2) & cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to be
executed. The prefetch unit will not execute this operation when the data to be prefetched is already in the data cache.
A prefr operation will not be executed when the cache is already occupied with 2 cache misses, when the operation is
issued.
The
prefr
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
execution of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is not
executed..
EXAMPLES
NOTE: This operation is supported only in TM1000, TM1100 and TM1300 and it is not
guaranteed to be available in future generations of this product.
Initial Values
Operation
Result
r10 = 0xabcd, r12 = 0xd
cache_block_size = 0x40
prefr r10 r12
Loads a cache line for the address space from
0xabc0 to 0x0xac3f from the main memory. If the
data is already in the cache, the operation is not exe-
cuted.
since guard is false, prefr operation is not executed
r10 = 0xabcd, r11 = 0, r12=0xd,
cache_block_size = 0x40
r10 = 0xabff, r11 = 1, r12 =0x1,
cache_block_size = 0x40
IF r11 prefr r10 r12
IF r11 prefr r10 r12
Loads a cache line for the address space from
0xac00 to 0x0xac3f from the main memory. If the
data is already in the cache, the operation is not exe-
cuted.
SEE ALSO
pref16x pref32x prefd
allocd allocr allocx
prefr