Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
81
7.2
Signal Summaries
Table 42
through
Table 45
list attributes of the Pentium II processor output, input, and I/O signals.
THERMTRIP#
O
The processor protects itself from catastrophic overheating by use of an internal thermal
sensor. This sensor is set well above the normal operating temperature to ensure that there
are no false trips. The processor will stop all execution when the junction temperature
exceeds approximately 135 °C. This is signaled to the system by the THERMTRIP#
(Thermal Trip) pin. Once activated, the signal remains latched, and the processor stopped,
until RESET# goes active. There is no hysteresis built into the thermal sensor itself; as long
as the die temperature drops below the trip level, a RESET# pulse will reset the processor
and execution will continue. If the temperature has not dropped below the trip level, the
processor will continue to drive THERMTRIP# and remain stopped.
TMS
I
The TMS (Test Mode Select) signal is a JTAG specification support signal used by debug
tools.
TRDY#
I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer. TRDY# must connect the appropriate
pins of all Pentium II processor system bus agents.
TRST#
I
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST# must be
driven low during power on Reset. This can be done with a 680 ohm pull-down resistor.
VID[4:0]
O
The VID[4:0] (Voltage ID) pins can be used to support automatic selection of power supply
voltages. These pins are not signals, but are either an open circuit or a short circuit to VSS
on the processor. The combination of opens and shorts defines the voltage required by the
processor. The VID pins are needed to cleanly support voltage specification variations on
Pentium II processors. See
Table 1
for definitions of these pins. The power supply must
supply the voltage that is requested by these pins, or disable itself.
Table 41. Signal Description (Sheet 8 of 8)
Name
Type
Description
Table 42. Output Signals
Name
Active Level
Clock
Signal Group
FERR#
Low
Asynch
CMOS Output
IERR#
Low
Asynch
CMOS Output
PRDY#
Low
BCLK
AGTL+ Output
SLOTOCC#
Low
Asynch
Power/Other
TDO
High
TCK
JTAG Output
THERMTRIP#
Low
Asynch
CMOS Output
VID[4:0]
High
Asynch
Power/Other