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| 型號： | pentium II cpu |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 33/84頁 |
| 文件大?。?/td> | 1092K |
| 代理商： | PENTIUM II CPU |
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Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
33
Note:
For
Figure 6
through
Figure 12
, the following apply:
1.
Figure 6
through
Figure 12
are to be used in conjunction with
Table 9
through
Table 20
.
2. All AC timings for the AGTL+ signals at the processor edge fingers are referenced to the
BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on
the processor substrate, allowing the processor core to receive the signal with a reference at
1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the
processor edge fingers.
3. All AC timings for the AGTL+ signals at the processor core pins are referenced to the BCLK
rising edge at 1.25 V. All GTL+ signal timings (address bus, data bus, etc.) are referenced at
1.00 V at the processor core pins.
4. All AC timings for the CMOS signals at the processor edge fingers are referenced to the
BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on
the processor substrate, allowing the processor core to receive the signal with a reference at
1.25 V. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the
processor edge fingers.
5. All AC timings for the APIC I/O signals at the processor edge fingers are referenced to the
PICCLK rising edge at 0.7 V. All APIC I/O signal timings are referenced at 1.25 V at the
processor edge fingers.
6. All AC timings for the TAP signals at the processor edge fingers are referenced to the TCK
rising edge at 0.70 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the
processor edge fingers.
Figure 5. BCLK to Core Logic Offset
BCLK at
Edge Fingers
000807
0.5V
BCLK at
Core Logic
1.25V
T7
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