- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369993 > pentium II cpu (Intel Corp.) Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) PDF資料下載
參數(shù)資料
| 型號： | pentium II cpu |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 79/84頁 |
| 文件大?。?/td> | 1092K |
| 代理商： | PENTIUM II CPU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁當(dāng)前第79頁第80頁第81頁第82頁第83頁第84頁
Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
79
PWRGOOD
I
The PWRGOOD (Power Good) signal is a 2.5 V tolerant processor input. The processor
requires this signal to be a clean indication that the clocks and power supplies (V
CC
,
etc.) are stable and within their specifications. Clean implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the power supplies
are turned on until they come within specification. The signal must then transition
monotonically to a high (2.5 V) state. The figure below illustrates the relationship of
PWRGOOD to other system signals. PWRGOOD can be driven inactive at any time, but
clocks and power must again be stable before a subsequent rising edge of PWRGOOD. It
must also meet the minimum pulse width specification in
Table 14
and
Table 15
, and be
followed by a 1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect internal
circuits against voltage sequencing issues. It should be driven high throughout boundary
scan operation.
PWRGOOD Relationship at Power-On
REQ[4:0]#
I/O
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all
Pentium II processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
RESET#
I
Asserting the RESET# signal resets all processors to known states and invalidates their L1
and L2 caches without writing back any of their contents. RESET# must remain active for
one microsecond for a “warm” Reset; for a power-on Reset, RESET# must stay active for at
least one millisecond after V
CC
and CLK have reached their proper specifications. On
observing active RESET#, all Pentium II processor system bus agents will deassert their
outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for
power-on configuration. These configuration options are described in the
P6 Family of
Processors Hardware Developer’s Manual
(Order Number 244001) for details.
The processor may have its outputs tristated via power-on configuration. Otherwise, if
INIT# is sampled active during the active-to-inactive transition of RESET#, the processor
will execute its Built-in Self-Test (BIST). Whether or not BIST is executed, the processor
will begin program execution at the power on Reset vector (default 0_FFFF_FFF0h).
RESET# must connect the appropriate pins of all Pentium II processor system bus agents.
RP#
I/O
The RP# (Request Parity) signal is driven by the request initiator, and provides parity
protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of all Pentium II
processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low if an
odd number of covered signals are low. This definition allows parity to be high when all
covered signals are high.
RS[2:0]#
I
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the appropriate
pins of all Pentium II processor system bus agents.
Table 41. Signal Description (Sheet 6 of 8)
Name
Type
Description
BCLK
PWRGOOD
RESET#
D0026-00
1 msec
V
IH,mn
V
CC
,
V
CCP
,
V
REF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium II processor | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。