- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369993 > pentium II cpu (Intel Corp.) Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) PDF資料下載
參數(shù)資料
| 型號： | pentium II cpu |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 10/84頁 |
| 文件大?。?/td> | 1092K |
| 代理商： | PENTIUM II CPU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
10
Datasheet
—
Volume III: System Programming Guide
(Order Number 243192)
P6 Family of Processors Hardware Developer’s Manual
(Order Number 244001)
Pentium
II Processor I/O Buffer Models
, Quad Format (developer.intel.com)
2.0
Electrical Specifications
2.1
Processor System Bus and V
REF
Most Pentium
II processor signals use a
variation
of the low voltage Gunning Transceiver Logic
(GTL) signaling technology.
The Pentium II processor system bus specification is similar to the GTL specification, but has been
enhanced to provide larger noise margins and reduced ringing. The improvements are
accomplished by increasing the termination voltage level and controlling the edge rates. This
specification is different from the standard GTL specification, and is referred to as
GTL+
. For
more information on GTL+ specifications, see AP-827,
100 MHz GTL+ Layout Guidelines for the
Pentium
II Processor and Intel
440BX AGPset
(Order Number 243735).
The Pentium II processor varies from the Pentium Pro processor in its output buffer
implementation. The buffers that drive most of the system bus signals on the Pentium II processor
are actively driven to V
CC
CORE
for one clock cycle after the low to high transition to improve its
rise times and reduce noise. These signals should still be considered open-drain and require
termination to a supply that provides the high signal level. Because this specification is different
from the standard GTL+ specification, it is referred to as Assisted Gunning Transitistor Logic
(AGTL+) in this document. AGTL+ logic and GTL+ logic are compatible with each other and may
both be used on the same system bus.
AGTL+ signals are open-drain and require termination to a supply that provides the high signal
level. AGTL+ inputs use differential receivers which require a reference signal (V
REF
). V
REF
is used
by the receivers to determine if a signal is a logical 0 or a logical 1, and is generated on the S.E.C
cartridges for the processor core. Local V
REF
copies should be generated on the motherboard for all
other devices on the AGTL+ system bus. Termination (usually a resistor at each end of the signal
trace) is used to pull the bus up to the high voltage level and to control reflections on the
transmission line. The processor contains termination resistors that provide termination for one end
of the Pentium II processor system bus. These specifications assume another resistor at the end of
each signal trace to ensure adequate signal quality for the AGTL+ signals; see
Table 8
for the bus
termination voltage specifications for AGTL+ and the
Pentium
II Processor Developer’s Manual
(Order Number 243502) for the GTL+ bus specification. Solutions exist for single-ended
termination as well, though solution space is affected.
Figure 2
is a schematic representation of
AGTL+ bus topology with Pentium II processors.
The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
Pentium II processor system bus including trace lengths is highly recommended when designing a
system with a heavily loaded AGTL+ bus, especially for systems using a single set of termination
resistors (i.e., those on the processor substrate) with the Intel
440BX AGPset. Such designs will
not match the solution space allowed for by installation of termination resistors on the
motherboard. See Intel’s World Wide Web page (http://developer.intel.com) to download the buffer
models:
Pentium
II Processor I/O Buffer Models,
Quad Format (Electronic Form
).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium II processor | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。