Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
21
NOTES:
1. Operating voltage is the voltage to which the component is designed to operate. See
Table 5
.
2. This rating applies to the V
CC
CORE
, V
CCL2
, V
CC
5
, and any input (except as noted below) to the processor.
3. Parameter applies to CMOS, APIC, and TAP bus signal groups only.
4. The mechanical integrity of the latch arms is specified to last a maximum of 50 cycles.
5. The electrical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion/extraction
cycles.
6. While insertion/extraction cycling above 50 insertions will cause an increase in the contact resistance (above 0.1
) and
a degradation in the material integrity of the edge finger gold plating, it is possible to have processor functionality above
the specified limit. The actual number of insertions before processor failure will vary based upon system configuration
and environmental conditions.
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the Pentium II processor edge
fingers. See
Section 7.0
for the processor edge finger signal definitions and
Section 5.0
for the
signal listing.
Most of the signals on the Pentium II processor system bus are in the AGTL+ signal group. These
signals are specified to be terminated to 1.5 V. The DC specifications for these signals are listed in
Table 6
.
To allow connection with other devices, the Clock, CMOS, APIC, and TAP signals are designed to
interface at non-AGTL+ levels. The DC specifications for these pins are listed in
Table 7
.
Table 5
through
Table 8
list the DC specifications for Pentium II processors operating at 100 MHz
processor system bus frequencies. Specifications are valid only while meeting specifications for
case temperature, clock frequency, and input voltages. Care should be taken to read all notes
associated with each parameter.
Table 4.
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
T
STORAGE
Processor storage temperature
–40
85
°C
V
CC(All)
Any processor supply voltage
with respect to V
SS
–0.5
Operating voltage + 1.0
V
1, 2
V
inAGTL
AGTL+ buffer DC input
voltage with respect to V
SS
–0.3
V
CC
CORE
+ 0.7
V
V
inCMOS
CMOS buffer DC input
voltage with respect to V
SS
–0.3
3.3
V
3
I
VID
Max VID pin current
5
mA
I
SLOTOCC
Max SLOTOCC# pin current
5
mA
Mech Max
Latch Arms
Mechanical integrity of latch
arms
50
Cycles
4
Mech Max Edge
Fingers
Mechanical integrity of
processor edge fingers
50
Insertions/
Extractions
5, 6