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| 型號： | pentium II cpu |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 78/84頁 |
| 文件大?。?/td> | 1092K |
| 代理商： | PENTIUM II CPU |
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Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
78
Datasheet
IGNNE#
I
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is
deasserted, the processor generates an exception on a noncontrol floating-point instruction
if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE
bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following
an I/O write instruction, it must be valid along with the TRDY# assertion of the
corresponding I/O Write bus transaction.
During active RESET#, the Pentium II processor begins sampling the A20M#, IGNNE#,
and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock
frequency. See
Table 9
. On the active-to-inactive transition of RESET#, the Pentium II
processor latches these signals and freezes the frequency ratio internally. System logic must
then release these signals for normal operation.
INIT#
I
The INIT# (Initialization) signal, when asserted, resets integer registers inside all processors
without affecting their internal (L1 or L2) caches or floating-point registers. Each processor
then begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT# assertion.
INIT# is an asynchronous signal and must connect the appropriate pins of all Pentium II
processor system bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the processor
executes its Built-in Self-Test (BIST).
LINT[1:0]
I
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all
APIC Bus agents, including all processors and the core logic or I/O APIC component. When
the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal,
and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor. Both signals are
asynchronous.
Both of these signals must be software configured via BIOS programming of the APIC
register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled
by default after Reset, operation of these pins as LINT[1:0] is the default configuration.
During active RESET#, the Pentium II processor begins sampling the A20M#, IGNNE#,
and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock
frequency. See
Table 9
. On the active-to-inactive transition of RESET#, the Pentium II
processor latches these signals and freezes the frequency ratio internally. System logic must
then release these signals for normal operation.
LOCK#
I/O
The LOCK# signal indicates to the system that a transaction must occur atomically. This
signal must connect the appropriate pins of all Pentium II processor system bus agents. For
a locked sequence of transactions, LOCK# is asserted from the beginning of the first
transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the Pentium II processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents
to retain ownership of the Pentium II processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
PICCLK
I
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or I/O
APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
PICD[1:0]
I/O
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message passing on the
APIC bus, and must connect the appropriate pins of all processors and core logic or I/O
APIC components on the APIC bus.
PRDY#
O
The PRDY (Probe Ready) signal is a processor output used by debug tools to determine
processor debug readiness.
PREQ#
I
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the
processors.
Table 41. Signal Description (Sheet 5 of 8)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium II processor | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
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