參數(shù)資料
型號(hào)： pentium II cpu
廠商： Intel Corp.
英文描述： Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器)
中文描述： 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器）
文件頁(yè)數(shù)： 80/84頁(yè)
文件大?。?/td> 1092K
代理商： PENTIUM II CPU
Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
80
Datasheet
RSP#
I
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible
for completion of the current transaction) during assertion of RS[2:0]#, the signals for
which RSP# provides parity protection. It must connect the appropriate pins of all Pentium
II processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low if an
odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this
indicates it is not being driven by any agent guaranteeing correct parity.
SLOTOCC#
O
The SLOTOCC# signal is defined to allow a system design to detect the presence of a
terminator card or processor in a SC 242 connector. Combined with the VID combination of
VID[4:0]= 11111 (see
Section 2.6
), a system can determine if a SC 242 connector is
occupied, and whether a processor core is present. See the table below for states and values
for determining the type of cartridge in the SC 242 connector.
SLP#
I
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to enter the
Sleep state. During Sleep state, the processor stops providing internal clock signals to all
units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will
not recognize snoops or interrupts. The processor will recognize only assertions of the
SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the
processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock
signals to the bus and APIC processor core units.
SMI#
I
The SMI# (System Management Interrupt) signal is asserted asynchronously by system
logic. On accepting a System Management Interrupt, processors save the current state and
enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and
the processor begins program execution from the SMM handler.
STPCLK#
I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops
providing internal clock signals to all processor core units except the bus and APIC units.
The processor continues to snoop bus transactions and service interrupts while in Stop-
Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all
units and resumes execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK
I
The TCK (Test Clock) signal provides the clock input for the Pentium II processor Test Bus
(also known as the Test Access Port).
TDI
I
The TDI (Test Data In) signal transfers serial test data into the Pentium II processor. TDI
provides the serial input needed for JTAG specification support.
TDO
O
The TDO (Test Data Out) signal transfers serial test data out of the Pentium II processor.
TDO provides the serial output needed for JTAG specification support.
TESTHI
I
The TESTHI signal must be connected to a 2.5 V power source through a 1-100 k
resistor
for proper processor operation.
THERMDN
O
Thermal Diode Cathode. Used to calculate core temperature. See
Section 4.1
.
THERMDP
I
Thermal Diode Anode. Used to calculate core temperature. See
Section 4.1
.
Table 41. Signal Description (Sheet 7 of 8)
Name
Type
Description
SC 242 Occupation Truth Table
Signal
Value
Status
SLOTOCC#
VID[4:0]
0
Anything other than
‘11111’
Processor with core in SC 242 connector.
SLOTOCC#
VID[4:0]
0
11111
Terminator cartridge in SC 242 connector
(i.e., no core present).
SLOTOCC#
VID[4:0]
1
Any value
SC 242 connector not occupied.
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