- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369993 > pentium II cpu (Intel Corp.) Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) PDF資料下載
參數(shù)資料
| 型號(hào)： | pentium II cpu |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 76/84頁 |
| 文件大?。?/td> | 1092K |
| 代理商： | PENTIUM II CPU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁當(dāng)前第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
76
Datasheet
BINIT#
I/O
The BINIT# (Bus Initialization) signal may be observed and driven by all Pentium II
processor system bus agents, and if used must connect the appropriate pins of all such
agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted
to signal any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled
asserted, all bus state machines are reset and any data which was in transit is lost. All agents
reset their rotating ID for bus arbitration to the state after Reset, and internal count
information is lost. The L1 and L2 caches are not affected.
If BINIT# observation is disabled during power-on configuration, a central agent may
handle an assertion of BINIT# as appropriate to the error handling architecture of the
system.
BNR#
I/O
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue
any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR
signal which must connect the appropriate pins of all Pentium II processor system bus
agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions
driven by multiple drivers, BNR# is activated on specific clock edges and sampled on
specific clock edges.
BP[3:2]#
I/O
The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the status of
breakpoints.
BPM[1:0]#
I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance.
BPRI#
I
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the Pentium II
processor system bus. It must connect the appropriate pins of all Pentium II processor
system bus agents. Observing BPRI# active (as asserted by the priority agent) causes all
other agents to stop issuing new requests, unless such requests are part of an ongoing locked
operation. The priority agent keeps BPRI# asserted until all of its requests are completed,
then releases the bus by deasserting BPRI#.
BR0#
BR1#
I/O
I
The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the system. The
BREQ[1:0]# signals are interconnected in a rotating manner to individual processor pins.
The table below gives the rotating interconnect between the processor and bus signals.
D[63:0]#
I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path
between the Pentium II processor system bus agents, and must connect the appropriate pins
on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
Table 41. Signal Description (Sheet 3 of 8)
Name
Type
Description
During power-up configuration, the central agent must assert the BR0# bus signal. All
symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of RESET#. Th
pin on which the agent samples an active level determines its agent ID. All agents then
configure their pins to match the appropriate bus signal protocol, as shown below.
BR[1:0]# Signal Agent IDs
BR0# (I/O) and BR1# Signals Rotating Interconnect
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
Pin Sampled Active in RESET#
Agent ID
BR0#
0
BR1#
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium II processor | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動(dòng)模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動(dòng)模塊處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。