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參數(shù)資料
| 型號(hào)： | pentium II cpu |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II處理器在450MHz（工作頻率450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 74/84頁 |
| 文件大?。?/td> | 1092K |
| 代理商： | PENTIUM II CPU |
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Pentium
II Processor at 350 MHz, 400 MHz, and 450 MHz
74
Datasheet
7.0
Pentium
II Processor Signal Description
This section provides an alphabetical listing of all Pentium II processor signals. The tables at the
end of this section summarize the signals by direction: output, input, and I/O.
7.1
Alphabetical Signals Reference
Table 41. Signal Description (Sheet 1 of 8)
Name
Type
Description
100/66#
I/O
This bidirectional signal is used to select the system bus frequency. A logic low will select a
66 MHz system bus frequency and a logic high (3.3 V) will select a 100 MHz system bus
frequency. The frequency is determined by the processor(s), PCIset, and frequency
synthesizer. All system bus agents must operate at the same frequency; in a two-way MP
Pentium
II procesor configuration, this signal must connect the pins of both Pentium II
processors. This signal will be grounded by processors that are only capable of operating at
a host frequency of 66 MHz. On motherboards which support operation at either 66- or
100 MHz, this signal must be pulled up to 3.3 V with a 200
resistor (as shown in the figure
below) and provided as a frequency selection signal to the clock driver/synthesizer. If the
system motherboard is not capable of operating at 100 MHz (e.g., Intel
440FX and 440LX
PCIset-based systems), it should ground this signal and generate a 66 MHz system bus
frequency. This signal can also be incorporated into RESET# logic on the motherboard if
only 100 MHz operation is supported (thus forcing the RESET# signal to remain active as
long as the 100/66# signal is low).
100/66# Pin Example
A[35:3]#
I/O
The A[35:3]# (Address) signals define a 2
36
-byte physical memory address space. When
ADS# is active, these pins transmit the address of a transaction; when ADS# is inactive,
these pins transmit transaction type information. These signals must connect the appropriate
pins of all agents on the Pentium II processor system bus. The A[35:24]# signals are parity-
protected by the AP1# parity signal, and the A[23:3]# signals are parity-protected by the
AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[35:3]# pins to
determine their power-on configuration. See the
Pentium
II Processor Developer’s
Manual
(Order Number 243502) for details.
3.3 Volts
100/66#
CK100
S
L
O
T
4
2
1
Processor
Core
GND
Pentium
II Processor
3.3 K
1 K
200
S
C
2
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