參數(shù)資料
型號: PCI1620PDV
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 97/164頁
文件大?。?/td> 720K
代理商: PCI1620PDV
4
29
4.41 Device Control Register
The device control register is provided for PCI1130 compatibility. It contains bits that are shared between functions
0 and 1. The interrupt mode select is programmed through this register. The socket-capable force bits are also
programmed through this register. See Table 4
16 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Device control
Type
RW
RW
RW
R
RW
RW
RW
RW
Default
0
1
1
0
0
1
1
0
Register:
Offset:
Type:
Default:
Device control
92h (Functions 0, 1)
Read-only, Read/Write
66h
Table 4
16. Device Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
SKTPWR_LOCK
RW
Socket power lock bit. When this bit is set to 1, software cannot power down the PC Card socket while
in D3. It may be necessary to lock socket power in order to support wake on LAN or RING if the
operating system is programmed to power down a socket when the CardBus controller is placed in the
D3 state.
6
3VCAPABLE
RW
3-V socket capable force bit.
0 = Not 3-V capable
1 = 3-V capable (default)
5
IO16R2
RW
Diagnostic bit. This bit defaults to 1.
4
3
RSVD
R
Reserved. This bit returns 0 when read. A write has no effect.
TEST
RW
TI test bit. Write only 0 to this bit.
2
1
§
INTMODE
RW
Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded:
00 = Parallel PCI interrupts only
01 = Reserved
10 = IRQ serialized interrupts and parallel PCI interrupts INTA and INTB
11 = IRQ and PCI serialized interrupts (default)
0
RSVD
RW
Reserved. Bit 0 is reserved for test purposes. Only a 0 should be written to this bit.
These bits are global in nature and should be accessed only through function 0.
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