參數(shù)資料
型號(hào)： PCI1620PDV
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 143/164頁
文件大?。?/td> 720K
代理商： PCI1620PDV
7
–
3
7.4
Status Register
This register provides device information to the host system. Bits in this register may be read normally. A bit in the
status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions
adhere to the definitions in the
PCI Local Bus Specification
. See Table 7
–
3 for a complete description of the register
contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Status
Type
RCU
RCU
RCU
RCU
RCU
R
R
RCU
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
Register:
Offset:
Type:
Default:
Status
06h
Read-only, Read/Clear/Update
0210h
Table 7
–
3. Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
PAR_ERR
RCU
Detected parity error. This bit is set when a parity error is detected, either an address- or data-
parity error.
14
SYS_ERR
RCU
Signaled system error. This bit is set when SERR is enabled and the PCI1620 has signaled a
system error to the host.
13
MABORT
RCU
Received master abort. This bit is set when a cycle initiated by the PCI1620 on the PCI bus
has been terminated by a master abort.
12
TABORT_REC
RCU
Received target abort. This bit is set when a cycle initiated by the PCI1620 on the PCI bus has
been terminated by a target abort.
11
TABORT_SIG
RCU
Signaled target abort. This bit is set by the PCI1620 when it terminates a transaction on the
PCI bus with a target abort.
10
–
9
PCI_SPEED
R
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating
that the PCI1620 asserts this signal at a medium speed on nonconfiguration cycle accesses.
8
DATAPAR
RCU
Data parity error detected. This bit is set when the following conditions have been met:
a. PERR was asserted by any PCI device, including the PCI1620.
b. The PCI1620 was the bus master during the data parity error.
c. The parity error response bit is set in the command register.
7
FBB_CAP
R
Fast back-to-back capable. The PCI1620 cannot accept fast back-to-back transactions;
thus, this bit is hardwired to 0.
6
UDF
R
UDF supported. The PCI1620 does not support the user definable features; thus, this bit is
hardwired to 0.
5
66MHZ
R
66-MHz capable. The PCI1620 operates at a maximum PCLK frequency of 33 MHZ; there-
fore, this bit is hardwired to 0.
4
CAPLIST
R
Capabilities list. This bit returns 1 when read, indicating that the firmware loading function of
the PCI1620 supports additional PCI capabilities.
3
–
0
RSVD
R
Reserved. These bits return 0s when read.
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