參數(shù)資料
型號(hào)： PCI1620PDV
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 140/164頁
文件大小： 720K
代理商： PCI1620PDV
6
–
8
Table 6
–
6.
Socket Control Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
2
–
0
VPPCTRL
RW
VPP control. These bits are used to request card VPP changes.
000 = Request power off (default)
001 = Request VPP = 12 V
010 = Request VPP = 5 V
011 = Request VPP = 3.3 V
100 = Request VPP = X.X V
101 = Request VPP = Y.Y V
110 = Reserved
111 = Reserved
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
6.6
Socket Power Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle. See Table 6
–
7 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Socket power management
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Socket power management
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket power management
CardBus Socket Address + 20h
Read-only, Read/Write
0000 0000h
Table 6
–
7. Socket Power Management Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
–
26
RSVD
R
Reserved. These bits return 0s when read.
25
SKTACCES
R
Socket access status. This bit provides information on whether a socket access has occurred. This bit is
cleared by a read access.
0 = No PC Card access has occurred (default).
1 = PC Card has been accessed.
Socket mode status. This bit provides clock mode information.
0 = Normal clock operation
1 = Clock frequency has changed.
24
SKTMODE
R
23
–
17
RSVD
R
These bits return 0s when read.
16
CLKCTRLEN
RW
CardBus clock control enable. This bit, when set, enables clock control according to bit 0 (CLKCTRL).
0 = Clock control disabled (default)
1 = Clock control enabled
15
–
1
RSVD
R
These bits return 0s when read.
0
CLKCTRL
RW
CardBus clock control. This bit determines whether the CardBus CLKRUN protocol attempts to stop or
slow the CardBus clock during idle states. The CLKCTRLEN bit enables this bit.
0 = Allows the CardBus CLKRUN protocol to attempt to stop the CardBus clock (default)
1 = Allows the CardBus CLKRUN protocol to attempt to slow the CardBus clock by a factor of 16
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