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參數(shù)資料
| 型號(hào)： | PCI1620PDV |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 46/164頁 |
| 文件大?。?/td> | 720K |
| 代理商： | PCI1620PDV |
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3
–
4
3.4.2
Serial EEPROM I
2
C Bus
The PCI1620 offers many choices for modes of operation, and these choices are selected by programming several
configuration registers. For system board applications, these registers are normally programmed through the BIOS
routine. For add-in card and docking-station/port-replicator applications, the PCI1620 provides a two-wire
inter-integrated circuit (IIC or I
2
C) serial bus for use with an external serial EEPROM.
The PCI1620 is always the bus master, and the EEPROM is always the slave. Either device can drive the bus low,
but neither device drives the bus high. The high level is achieved through the use of pullup resistors on the SCL and
SDA signal lines. The PCI1620 is always the source of the clock signal, SCL.
System designers who wish to load register values with a serial EEPROM must use a pulldown resistor on the LATCH
terminal. If the PCI1620 detects a logic-low level on the LATCH terminal at the end of GRST, it initiates incremental
reads from the external EEPROM. Any size serial EEPROM up to the I
2
C limit of 16 Kbits can be used, but only the
first 42 bytes are required to configure the PCI1620. Figure 3
–
3 shows a 2-Kbit serial EEPROM application.
SCL/MFUNC4
SDA/MFUNC1
VCC
A0
A1
A2
SCL
SDA
PCI1620
Serial
EEPROM
LATCH
Figure 3
–
3. Serial EEPROM Application
In addition to loading configuration data from an EEPROM, the PCI1620 I
2
C bus can be used to read and write from
other I
2
C serial devices. A system designer can control the I
2
C bus, using the PCI1620 as bus master, by reading
and writing PCI configuration registers
. Setting the SBDETECT bit (bit 3) in the serial bus control/status register (PCI
offset B3h, see Section 4.52) causes the PCI1620 to multiplex the SDA and SCL signals to the MFUNC1 and
MFUNC4 terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by
accessing the serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1, and B2h;
see Sections 4.49, 4.50, and 4.51, respectively).
EEPROM interface status information is communicated through the serial bus control and status register (PCI offset
B3h, see Section 4.52). Bit 2 (EEDETECT) in this register indicates whether or not the PCI1620 serial EEPROM
circuitry detects the pulldown resistor on LATCH. Any undefined condition, such as a missing acknowledge, results
in bit 1 (DATAERR) being set. Bit 0 (EEBUSY) is set while the subsystem ID register is loading (serial EEPROM
interface is busy).
3.4.3
PCI1620 EEPROM Map
The mapping of the PCI configuration, CardBus, and ExCA register bits that can be loaded from a serial EEPROM
is shown in Table 3
–
1. The PCI 1620 starts at EEPROM address zero and continues to read incrementally the 42
bytes of data. The first byte at EEPROM address 00h is a flag byte with the value 01h. Whenever a serial EEPROM
is used to load registers, all 42 bytes of data must be programmed in order, as shown in Table 3
–
1.
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