參數(shù)資料
型號: PCI1620PDV
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 50/164頁
文件大小: 720K
代理商: PCI1620PDV
3
8
Table 3
5. Query Terminals
Media Interface Implementation
SQRY6
SQRY5
SQRY4
SQRY3
INTERFACE IMPLEMENTATION
0
0
0
0
Reserved
0
0
0
1
SmartMedia interface
0
0
1
0
MMC/SD interface
0
0
1
1
Memory stick interface
0
1
0
0
Smart card interface
0
1
0
1
Reserved
0
1
1
X
Reserved
1
X
X
X
Reserved
SQRYDRV
SQRY1
SQRY2
SQRY3
SQRY4
SQRY5
SQRY6
SQRY7
SQRY8
SQRY9
SQRY10
UltraMedia Adapter and Card
10 k
PCI1620 UltraMedia Controller
Figure 3
4. Example SmartMedia Query Terminal Configuration
When the query process has completed, the PCI1620 updates its internal registers and signals the card insertion to
the host. The SQRY[10:1] terminals are switched to ground. UltraMedia devices are reported as 5-V, 16-bit cards
through the socket present state register (CardBus offset 08h, see Section 6.3). The host requests that 5-V power
be applied the socket, and the PCI1620 automatically overrides this request and signals the TI TPS222x power switch
for the appropriate voltage levels (V
CC
and V
PP
) determined from the query process.
3.5.2
Query Terminals
The UltraMedia query terminal assignments and definitions are listed in Table 3
3 through Table 3
5. If a 1 value is
needed for a query terminal, that terminal is connected to the query driver terminal. If a 0 value is needed for a query
terminal, that terminal is connected to ground.
As an example, Figure 3
4 shows the query terminal configuration for a 3.3-V V
CC
and 1.8-V V
CORE
UltraMedia card
with a SmartMedia interface.
3.5.3
P
2
C Power Switch Interface
The PCI1620 provides a 3-wire serial PCMCIA-to-peripheral control (P
2
C) interface for use with TI TPS222x dual-slot
PC Card power-interface switches. The clock signal, CLOCK, can be derived from the PCI clock and driven by the
PCI1620, or supplied from an external 32-kHz oscillator. Selection of the clock source is controlled by bit 27, P2CCLK,
in the system control register (PCI offset 80h, see Section 4.31). No additional support is required to utilize the P
2
C
interface.
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