參數(shù)資料
型號: PCI1620PDV
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 73/164頁
文件大?。?/td> 720K
代理商: PCI1620PDV
4
5
4.6
Revision ID Register
The revision ID register indicates the silicon revision of the PCI1620.
Bit
7
6
5
4
3
2
1
0
Name
Revision ID
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Default:
Revision ID
08h (functions 0, 1)
Read-only
01h
4.7
Class Code Register
The class code register recognizes PCI1620 functions 0 and 1 as a bridge device (06h) and a CardBus bridge device
(07h), with a 00h programming interface.
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
PCI class code
Base class
Subclass
Programming interface
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
PCI class code
09h (functions 0, 1)
Read-only
06 0700h
4.8
Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit
7
6
5
4
3
2
1
0
Name
Cache line size
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Cache line size
0Ch (Functions 0, 1)
Read/Write
00h
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