參數(shù)資料
型號: PCI1620PDV
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 125/164頁
文件大小: 720K
代理商: PCI1620PDV
5
19
5.16 ExCA Memory Windows 0
4 End-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23
A20 of the end address. In addition, the memory
window wait states are set in this register. See Table 5
12 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
ExCA memory windows 0
4 end-address high-byte
Type
RW
RW
R
R
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Register:
Offset:
ExCA memory window 0 end-address high-byte
CardBus Socket Address + 813h:
Card A ExCA Offset 13h
Card B ExCA Offset 53h
Register:
Offset:
ExCA memory window 1 end-address high-byte
CardBus Socket Address + 81Bh:
Card A ExCA Offset 1Bh
Card B ExCA Offset 5Bh
Register:
Offset:
ExCA memory window 2 end-address high-byte
CardBus Socket Address + 823h:
Card A ExCA Offset 23h
Card B ExCA Offset 63h
Register:
Offset:
ExCA memory window 3 end-address high-byte
CardBus Socket Address + 82Bh:
Card A ExCA Offset 2Bh
Card B ExCA Offset 6Bh
Register:
Offset:
ExCA Memory window 4 end-address high-byte
CardBus Socket Address + 833h:
Card A ExCA Offset 33h
Card B ExCA Offset 73h
Type:
Default:
Read/Write, Read-only
00h
Table 5
12. ExCA Memory Windows 0
4 End-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
7
6
MEMWS
RW
Wait state. These bits specify the number of equivalent ISA wait states to be added to 16-bit memory
accesses. The number of wait states added is equal to the binary value of these 2 bits.
5
4
RSVD
R
Reserved. These bits return 0s when read. Writes have no effect.
3
0
ENDHN
RW
End-address high nibble. These bits represent the upper address bits A23
A20 of the memory window end
address.
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