參數(shù)資料
型號： PCI1620PDV
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 93/164頁
文件大?。?/td> 720K
代理商： PCI1620PDV
4
–
25
4.38 Multifunction Routing Status Register
The multifunction routing status register is used to configure the MFUNC6
–
MFUNC0 terminals. These terminals may
be configured for various functions. This register is intended to be programmed once at power-on initialization. The
default value for this register can also be loaded through a serial EEPROM. See Table 4
–
13 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Multifunction routing status
Type
R
RW
RW
RW
R
RW
RW
RW
R
RW
RW
RW
R
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Multifunction routing status
Type
R
RW
RW
RW
R
RW
RW
RW
R
RW
RW
RW
R
RW
RW
RW
Default
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Multifunction routing status
8Ch
Read/Write, Read-only
0000 1000h
Table 4
–
13. Multifunction Routing Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
–
28
RSVD
R
Bits 31
–
28 return 0s when read.
27
–
24
MFUNC6
RW
Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal
as follows:
0000 = RSVD
0100 = IRQ4
1000 = IRQ8
0001 = CLKRUN
0101 = IRQ5
1001 = IRQ9
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
0011 = IRQ3
0111 = IRQ7
1011 = RSVD
1100 = IRQ12
1101 = IRQ13
1110 = IRQ14
1111 = IRQ15
23
–
20
MFUNC5
RW
Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal
as follows:
0000 = GPI4
0100 = IRQ4
1000 = CAUDPWM
0001 = GPO4
0101 = IRQ5
1001 = IRQ9
0010 = PCGNT
0110 = ZVSTAT
1010 = IRQ10
0011 = IRQ3
0111 = ZVSEL1
1011 = RSVD
1100 = LEDA1
1101 = LED_SKT
1110 = GPE
1111 = IRQ15
19
–
16
MFUNC4
RW
Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal
as follows:
NOTE: When the (EEPROM) serial bus mode is implemented by pulling down the LATCH terminal, the
SBDETECT bit in the serial bus control and status register (PCI offset B3h, see Section 4.52) is set
and the MFUNC4 terminal is used to provide the SCL signalling; MFUNC4 is not available for the
following signals while the SBDETECT bit is set.
0000 = GPI3
0001 = GPO3
0010 = LOCK PCI
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL1
1000 = CAUDPWM
1001 = IRQ9
1010 = RSVD
1011 = IRQ11
1100 = RI_OUT
1101 = LED_SKT
1110 = GPE
1111 = IRQ15
15
–
12
MFUNC3
RW
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal
as follows:
0000 = RSVD
0100 = IRQ4
1000 = IRQ8
0001 = IRQSER
0101 = IRQ5
1001 = IRQ9
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1100 = IRQ12
1101 = IRQ13
1110 = IRQ14
1111 = IRQ15
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