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參數(shù)資料
| 型號(hào)： | PCI1620PDV |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 53/164頁(yè) |
| 文件大?。?/td> | 720K |
| 代理商： | PCI1620PDV |
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3
–
11
Table 3
–
6. Functionality of the ZV Output Signals
INPUTS
OUTPUTS
PORTSEL
X
SOCKET A ENABLE
0
SOCKET B ENABLE
0
ZVSEL0
1
ZVSEL1
1
ZVSTAT
0
0
1
X
0
1
1
0
0
1
1
0
1
1
X
1
1
0
1
1
1
0
0
1
1
Also shown in Figure 3
–
7 is a third ZV input that can be provided from a source such as a high-speed serial bus like
IEEE 1394. The ZVSTAT signal provides a mechanism to switch the third ZV source. ZVSTAT is an active-high output
indicating that one of the PCI1620 sockets is enabled for ZV mode. The implementation shown in Figure 3
–
7 can be
used if PC Card ZV is prioritized over other sources.
3.5.5
Standardized Zoomed-Video Register Model
The standardized zoomed video register model is defined for the purpose of standardizing the ZV port control for PC
Card controllers across the industry. The following list summarizes the standardized zoomed-video register model
changes to the existing PC Card register set.
Socket present state register (CardBus socket address + 08h, see Section 6.3)
Bit 27 (ZVSUPPORT) has been added. The platform BIOS can set this bit via the socket force event register
(CardBus socket address + 0Ch, see Section 6.4) to define whether zoomed video is supported on that
socket by the platform.
Socket force event register (CardBus socket address + 0Ch, see Section 6.4)
Bit 27 (FZVSUPPORT) has been added. The platform BIOS can use this bit to set the ZVSUPPORT bit in
the socket present state register (CardBus socket address + 08h, see Section 6.3) to define whether
zoomed video is supported on that socket by the platform.
Socket control register (CardBus socket address +10h, see Section 6.5)
Bit 11 (ZV_ACTIVITY) has been added. This bit is set when zoomed video is enabled for either of the PC
Card sockets.
Bit 10 (STDZVREG) has been added. This bit defines whether the PC Card controller supports the
standardized zoomed-video register model.
Bit 9 (ZVEN) is provided for software to enable or disable zoomed video, per socket.
If the STDZVEN bit (bit 0) in the diagnostic register (PCI offset 93h, see Section 4.42) is 1, then the standardized
zoomed video register model is disabled. For backward compatibility, even if the STDZVEN bit is 0 (enabled), the
PCI1620 allows software to access zoomed video through the legacy address in the card control register (PCI offset
91h, see Section 4.40), or through the new register model in the socket control register (CardBus socket address +
10h, see Section 6.5).
3.5.6
Integrated Pullup Resistors
The
PC Card Standard
requires pullup resistors on various terminals to support both CardBus and 16-bit PC Card
configurations. Table 3
–
7 lists these terminals. The PCI1620 has integrated all of these pullup resistors and requires
no additional external components. The I/O buffer on the BVD1(STSCHG)/CSTSCHG terminal has the capability to
switch to an internal pullup resistor when a 16-bit PC Card is inserted, or switch to an internal pulldown resistor when
a CardBus card is inserted. This prevents inadvertent CSTSCHG events. The pullup resistor requirements for the
various UltraMedia interfaces are either included in the UltraMedia cards (or the UltraMedia adapter) or are part of
the existing PCMCIA architecture. The PCI1620 does not require any additional components for UltraMedia support.
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