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參數(shù)資料
| 型號(hào)： | PCI1620PDV |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 72/164頁(yè) |
| 文件大?。?/td> | 720K |
| 代理商： | PCI1620PDV |
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4
–
4
4.5
Status Register
The status register provides device information to the host system. Bits in this register can be read normally. A bit
in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit
functions adhere to the definitions in the
PCI Bus Specification
, as seen in the bit descriptions. PCI bus status is shown
through each function. See Table 4
–
3 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Status
Type
RW
RW
RW
RW
RW
R
R
RW
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
Register:
Offset:
Type:
Default:
Status
06h (Functions 0, 1)
Read-only, Read/Write
0210h
Table 4
–
3. Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
PAR_ERR
RW
Detected parity error. This bit is set when a parity error is detected, either an address or data parity error.
Write a 1 to clear this bit.
14
SYS_ERR
RW
Signaled system error. This bit is set when SERR is enabled and the PCI1620 signaled a system error to
the host. Write a 1 to clear this bit.
13
MABORT
RW
Received master abort. This bit is set when a cycle initiated by the PCI1620 on the PCI bus has been
terminated by a master abort. Write a 1 to clear this bit.
12
TABT_REC
RW
Received target abort. This bit is set when a cycle initiated by the PCI1620 on the PCI bus was terminated
by a target abort. Write a 1 to clear this bit.
11
TABT_SIG
RW
Signaled target abort. This bit is set by the PCI1620 when it terminates a transaction on the PCI bus with
a target abort. Write a 1 to clear this bit.
10
–
9
PCI_SPEED
R
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the
PCI1620 asserts this signal at a medium speed on nonconfiguration cycle accesses.
8
DATAPAR
RW
Data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. PERR was asserted by any PCI device including the PCI1620.
b. The PCI1620 was the bus master during the data parity error.
c. The parity error response bit is set in the command register.
7
FBB_CAP
R
Fast back-to-back capable. The PCI1620 cannot accept fast back-to-back transactions; thus, this bit is
hardwired to 0.
6
UDF
R
UDF supported. The PCI1620 does not support user-definable features; therefore, this bit is hardwired to
0.
5
66MHZ
R
66-MHz capable. The PCI1620 operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is
hardwired to 0.
4
CAPLIST
R
Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI
capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this
function.
3
–
0
RSVD
R
These bits return 0s when read.
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