參數(shù)資料
型號： PCI1620PDV
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 69/164頁
文件大?。?/td> 720K
代理商： PCI1620PDV
4
–
1
4 PC Card Controller Programming Model
This chapter describes the PCI1620 PCI configuration registers that make up the 256-byte PCI configuration header
for each PCI1620 function. There are some bits which affect both CardBus functions, but which, in order to work
properly, must be accessed only through function 0. These are called global bits. Registers containing one or more
global bits are denoted by
§
in Table 4
–
1.
Any bit followed by a
is not cleared by the assertion of PRST (see
CardBus Device Class Power Management
,
Section NO TAG, for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are cleared only
by GRST. If PME is not enabled, then these bits are cleared by GRST or PRST. These bits are sometimes referred
to as PME context bits and are implemented to allow PME context to be preserved during the transition from D3
hot
or D3
cold
to D0. If the PME context PRST functionality is not desired, then the PRST and GRST signals should be
tied together.
If a bit is followed by a
, then this bit is cleared only by GRST in all cases (not conditional on PME being enabled).
These bits are intended to maintain device context such as interrupt routing and MFUNC programming during warm
resets.
4.1
PCI Configuration Registers (Functions 0 and 1)
The PCI1620 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. The
configuration header, compliant with the
PCI Local Bus Specification
as a CardBus bridge header, is
PC99/PC2001
compliant as well. Table 4
–
1 illustrates the PCI configuration register map, which includes both the predefined portion
of the configuration space and the user-definable registers.
Table 4
–
1. Functions 0 and 1 PCI Configuration Register Map
REGISTER NAME
OFFSET
Device ID
Vendor ID
00h
Status
Command
04h
Class code
Revision ID
08h
BIST
Header type
Latency timer
Cache line size
0Ch
CardBus socket registers/ExCA base address register
10h
Secondary status
Reserved
Capability pointer
14h
CardBus latency timer
Subordinate bus number
CardBus bus number
PCI bus number
18h
CardBus memory base register 0
1Ch
CardBus memory limit register 0
20h
CardBus memory base register 1
24h
CardBus memory limit register 1
28h
CardBus I/O base register 0
2Ch
CardBus I/O limit register 0
30h
CardBus I/O base register 1
34h
CardBus I/O limit register 1
38h
Bridge control
Subsystem ID
Interrupt pin
Interrupt line
3Ch
Subsystem vendor ID
40h
PC Card 16-bit I/F legacy-mode base-address
Reserved
44h
48h
–
68h
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
One or more bits in this register are cleared only by the assertion of GRST.
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