參數(shù)資料
型號： PCI1620PDV
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 28/164頁
文件大?。?/td> 720K
代理商： PCI1620PDV
2
–
12
The terminals are grouped in tables by functionality, such as PCI system function and power supply function, for quick
reference (see Table 2
–
5 through Table 2
–
15). The terminal names and numbers are also listed for convenient
reference.
Table 2
–
5. Power Supply Terminals
TERMINAL
NAME
NO.
I/O
DESCRIPTION
PDV
GHK
GND
6, 24, 43, 62,
95, 110, 147,
166, 185, 199
A06, A09, A14,
E01, F19, K01,
P01, R19, W06,
W14
A07, A12, G01,
G19, J19, N01,
N19, W08, W13
P19
R01
A10
L01
K19
–
Device ground terminals
VCC
14, 39, 70, 91,
118, 133, 143,
174, 195
114
47
180
29
128
–
3.3-V power terminals
VCCA
VCCB
VCCP
VR_EN
VR_OUT
–
–
–
I
O
PC Card A signaling rail power input; clamped per PC Card specification
PC Card B signaling rail power input; clamped per PC Card specification
PCI signaling clamp rail power input; clamped per PCI specification
Internal voltage regulator enable. Active-low
Internal voltage regulator output (1.8 V) for external bypass capacitor
Table 2
–
6. PC Card Power Switch Terminals
TERMINAL
NAME
NO.
I/O
DESCRIPTION
PDV
GHK
CLOCK
154
F15
I/O
Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults
to an input, but can be changed to a PCI1620 output by using bit 27 (P2CCLK) in the system control register
(PCI offset 80h, see Section 4.31). For use with the TPS222X, the maximum frequency of this signal is limited
to 2 MHz. However, the PCI1620 requires a 16-KHz to 100-KHz frequency range. As an input, this terminal
requires an external 32-kHz clock. If a system design defines this terminal as an output, then this terminal
requires an external pulldown resistor. The frequency of the PCI1620 output CLOCK is derived from the
internal ring oscillator (16 kHz typical).
DATA
155
E17
O
Power switch data. DATA is used to communicate socket power control information serially to the power
switch.
LATCH
153
E18
I/O
Power switch latch. LATCH is asserted by the PCI1620 to indicate to the power switch that the data on the
DATA line is valid. The LATCH terminal is also used to indicate the presence of an external EEPROM; when
a pulldown resistor is implemented on this terminal, the MFUNC1 and MFUNC4 terminals provide the serial
EEPROM SDA and SCL interface.
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