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| 型號： | PCI1520-EP |
| 英文描述： | Military Enhanced Plastic PC Card Controllers Data Manual |
| 中文描述： | 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 97/125頁 |
| 文件大?。?/td> | 716K |
| 代理商： | PCI1520-EP |
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5
–
10
5.6
ExCA Card Status-Change Interrupt Configuration Register
The ExCA card status-change interrupt configuration register controls interrupt routing for card status-change
interrupts, as well as masking CSC interrupt sources. See Table 5
–
8 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
ExCA status-change-interrupt configuration
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Register:
Offset:
ExCA card status-change interrupt configuration
CardBus socket address + 805h; Card A ExCA offset 05h
Card B ExCA offset 45h
Type:
Default:
Read/Write
00h
Table 5
–
8. ExCA Card Status-Change Interrupt Configuration Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
–
4
CSCSELECT
RW
Interrupt select for card status change. Bits 7
–
4 select the interrupt routing for card status-change
interrupts.
0000 = CSC interrupts routed to PCI interrupts if bit 5 (CSC) of the diagnostic register (PCI offset 93h, see
Section 4.34) is set to 1. In this case bit 4 (CSCROUTE) of the ExCA interrupt and general control register
(ExCA offset 03h/43h/803h, see Section 5.4) is a don
’
t care. This is the default setting.
0000 = No ISA interrupt routing if bit 5 (CSC) of the diagnostic register is set to 0 (see Section 4.34). In
this case, CSC interrupts are routed to PCI interrupts by setting bit 4 (CSCROUTE) of the ExCA interrupt
and general control register (ExCA offset 03h/43h/803h, see Section 5.4) to 1.
This field is encoded as:
0000 = No interrupt routing (default)
1000 = IRQ8 enabled
0001 = IRQ1 enabled
1001 = IRQ9 enabled
0010 = SMI enabled
1010 = IRQ10 enabled
0011 = IRQ3 enabled
1011 = IRQ11 enabled
0100 = IRQ4 enabled
1100 = IRQ12 enabled
0101 = IRQ5 enabled
1101 = IRQ13 enabled
0110 = IRQ6 enabled
1110 = IRQ14 enabled
0111 = IRQ7 enabled
1111 = IRQ15 enabled
3
CDEN
RW
Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as:
0 = Disables interrupts on CD1 or CD2 line changes (default)
1 = Enables interrupts on CD1 or CD2 line changes
2
READYEN
RW
Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host
interrupt. This interrupt source is considered a card status change. This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
1
BATWARNEN
RW
Battery warning enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
0
BATDEADEN
RW
Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
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