參數(shù)資料
型號： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強塑料PC卡控制器數(shù)據(jù)手冊
文件頁數(shù)： 56/125頁
文件大小： 716K
代理商： PCI1520-EP
4
–
3
4.4
Command Register
The command register provides control over the PCI1520 interface to the PCI bus. All bit functions adhere to the
definitions in
PCI Local Bus Specification
. None of the bit functions in this register is shared between the two PCI1520
PCI functions. Two command registers exist in the PCI1520, one for each function. Software must manipulate the
two PCI1520 functions as separate entities when enabling functionality through the command register. The
SERR_EN and PERR_EN enable bits in this register are internally wired-OR between the two functions, and these
control bits appear separately according to their software function. See Table 4
–
3 for a complete description of the
register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Command
Type
R
R
R
R
R
R
R
RW
R
RW
RW
R
R
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Command
04h
Read-only, Read/Write
0000h
Table 4
–
3. Command Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
–
10
RSVD
R
Reserved. Bits 15
–
10 return 0s when read.
9
FBB_EN
R
Fast back-to-back enable. The PCI1520 does not generate fast back-to-back transactions; therefore, bit 9
returns 0 when read.
8
SERR_EN
RW
System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can
be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 must be set for the
PCI1520 to report address parity errors.
0 = Disable SERR output driver (default)
1 = Enable SERR output driver
7
STEP_EN
R
Address/data stepping control. The PCI1520 does not support address/data stepping; therefore, bit 7 is
hardwired to 0.
6
PERR_EN
RW
Parity error response enable. Bit 6 controls the PCI1520 response to parity errors through PERR. Data parity
errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting SERR.
0 = PCI1520 ignores detected parity error (default)
1 = PCI1520 responds to detected parity errors
5
VGA_EN
RW
VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette
registers.
4
MWI_EN
R
Memory write-and-invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory
write-and-Invalidate commands. The PCI1520 controller does not support memory write-and-invalidate
commands, but uses memory write commands instead; therefore, this bit is hardwired to 0.
3
SPECIAL
R
Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1520 does
not respond to special cycle operations; therefore, this bit is hardwired to 0.
2
MAST_EN
RW
Bus master control. Bit 2 controls whether or not the PCI1520 can act as a PCI bus initiator (master). The
PCI1520 can take control of the PCI bus only when this bit is set.
0 = Disables the PCI1520 from generating PCI bus accesses (default)
1 = Enables the PCI1520 to generate PCI bus accesses
1
MEM_EN
RW
Memory space enable. Bit 1 controls whether or not the PCI1520 can claim cycles in PCI memory space.
0 = Disables the PCI1520 from responding to memory space accesses (default)
1 = Enables the PCI1520 to respond to memory space accesses
0
IO_EN
RW
I/O space control. Bit 0 controls whether or not the PCI1520 can claim cycles in PCI I/O space.
0 = Disables the PCI1520 from responding to I/O space accesses (default)
1 = Enables the PCI1520 to respond to I/O space accesses
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