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| 型號： | PCI1520-EP |
| 英文描述： | Military Enhanced Plastic PC Card Controllers Data Manual |
| 中文描述： | 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 52/125頁 |
| 文件大?。?/td> | 716K |
| 代理商： | PCI1520-EP |
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3
–
24
The specific issues addressed by the
PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
for D3 wake up are as follows:
Preservation of device context. The specification states that a reset must occur during the transition from
D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear
the PME context registers.
Power source in D3
cold
if wake-up support is required from this state.
The Texas Instruments PCI1520 addresses these D3 wake-up issues in the following manner:
Two resets are provided to handle preservation of PME context bits:
–
Global reset (GRST) is used only on the initial boot up of the system after power up. It places the
PCI1520 in its default state and requires BIOS to configure the device before becoming fully functional.
–
PCI reset (PRST) has dual functionality based on whether PME is enabled or not. If PME is enabled,
then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset.
Please see the master list of PME context bits in Section 3.8.11.
Power source in D3
cold
if wake-up support is required from this state. Since V
CC
is removed in D3
cold
, an
auxiliary power source must be supplied to the PCI1520 V
CC
terminals. Consult the
PCI14xx
Implementation Guide for D3 Wake-Up
or the
PCI Power Management Interface Specification for PCI to
CardBus Bridges
for further information.
3.8.10 ACPI Support
The
Advanced Configuration and Power Interface (ACPI) Specification
provides a mechanism that allows unique
pieces of hardware to be described to the ACPI driver. The PCI1520 offers a generic interface that is compliant with
ACPI design rules.
Two doublewords of general-purpose ACPI programming bits reside in PCI1520 PCI configuration space at offset
A8h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event
status and enable bits reside in the general-purpose event status register (PCI offset A8h, see Section 4.41) and
general-purpose event enable register (PCI offset AAh, see Section 4.42). The status and enable bits are
implemented as defined by ACPI and illustrated in Figure 3
–
17.
Event Output
Event Input
Enable Bit
Status Bit
Figure 3
–
17. Block Diagram of a Status/Enable Cell
The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the
pending status bit. The control method can then control the hardware by manipulating the hardware control bits or
by investigating child status bits and calling their respective control methods. A hierarchical implementation would
be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report
events.
For more information of ACPI, see the
Advanced Configuration and Power Interface (ACPI) Specification.
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| PCI1620PDV | Controller Miscellaneous - Datasheet Reference |
| PCI2050A | 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge |
| PCI2050GHK | BUS CONTROLLER |
| PCI2050PDV | BUS CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI1520GHK | 功能描述:外圍驅(qū)動器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| PCI1520IPDV | 功能描述:外圍驅(qū)動器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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