參數(shù)資料
型號(hào): PCI1520-EP
英文描述: Military Enhanced Plastic PC Card Controllers Data Manual
中文描述: 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊(cè)
文件頁(yè)數(shù): 120/125頁(yè)
文件大?。?/td> 716K
代理商: PCI1520-EP
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6
9
6.6
Socket Power-Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle. See Table 6
7 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Socket power-management
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Socket power-management
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Socket power-management
Read-only, Read/Write
CardBus socket address + 20h
0000 0000h
Table 6
7. Socket Power-Management Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
26
RSVD
R
Reserved. Bits 31
26 return 0s when read.
25
SKTACCES
R
Socket access status. This bit provides information on when a socket access has occurred. This bit is
cleared by a read access.
0 = A PC card access has not occurred (default).
1 = A PC card access has occurred.
24
SKTMODE
R
Socket mode status. This bit provides clock mode information.
0 = Clock is operating normally.
1 = Clock frequency has changed.
23
17
RSVD
R
Reserved. Bits 23
17 return 0s when read.
16
CLKCTRLEN
RW
CardBus clock control enable. When bit 16 is set, bit 0 (CLKCTRL) is enabled.
0 = Clock control is disabled (default).
1 = Clock control is enabled.
15
1
RSVD
R
Reserved. Bits 15
1 return 0s when read.
0
CLKCTRL
RW
CardBus clock control. This bit determines whether the CB CLKRUN protocol stops or slows the CB clock
during idle states. Bit 16 (CLKCTRLEN) enables this bit.
0 = Allows CB CLKRUN protocol to stop the CB clock (default).
1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16.
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