參數(shù)資料
型號： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強塑料PC卡控制器數(shù)據(jù)手冊
文件頁數(shù)： 108/125頁
文件大?。?/td> 716K
代理商： PCI1520-EP
5
–
21
5.19 ExCA Card Detect and General Control Register
The ExCA card detect and general control register controls how the ExCA registers for the socket respond to card
removal, as well as reports the status of VS1 and VS2 at the PC Card interface. See Table 5
–
14 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
ExCA I/O card detect and general control
Type
R
R
RW
RW
R
R
RW
R
Default
X
X
0
0
0
0
0
0
Register:
Offset:
ExCA card detect and general control
CardBus socket address + 816h; Card A ExCA offset 16h
Card B ExCA offset 56h
Type:
Default:
Read-only, Read/Write
XX00 0000b
Table 5
–
14. ExCA Card Detect and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
VS2STAT
R
VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, does not have
a default value.
0 = VS2 low
1 = VS2 high
6
VS1STAT
R
VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, does not have
a default value.
0 = VS1 low
1 = VS1 high
5
SWCSC
RW
Software card detect interrupt. If bit 3 (CDEN) in the ExCA card status-change interrupt configuration
register (ExCA offset 05h/45h/805, see Section 5.6) is set, then writing a 1 to bit 5 causes a card-detect
card-status change interrupt for the associated card socket. If bit 3 (CDEN) in the ExCA card
status-change-interrupt configuration register (ExCA offset 05h/45h/805, see Section 5.6) is cleared to 0,
then writing a 1 to bit 5 has no effect. A read operation of this bit always returns 0.
4
CDRESUME
RW
Card detect resume enable. If bit 4 is set to 1, then once a card detect change has been detected on CD1
and CD2 inputs, RI_OUT goes from high to low. RI_OUT remains low until bit 0 (card status change) in
the ExCA card status-change register is cleared (see Section 5.5). If this bit is a 0, then the card detect
resume functionality is disabled.
0 = Card detect resume disabled (default)
1 = Card detect resume enabled
3
–
2
RSVD
R
Reserved. Bits 3 and 2 return 0s when read.
1
REGCONFIG
RW
Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card
removal event. This bit is encoded as:
0 = No change to ExCA registers on card removal (default)
1 = Reset ExCA registers on card removal
0
RSVD
R
Reserved. Bit 0 returns 0 when read.
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相關代理商/技術參數(shù)
參數(shù)描述
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