參數(shù)資料
型號： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強塑料PC卡控制器數(shù)據(jù)手冊
文件頁數(shù)： 82/125頁
文件大小： 716K
代理商： PCI1520-EP
4
–
29
4.41 General-Purpose Event Status Register
The general-purpose event status register contains status bits that are set when events occur that are controlled by
the general-purpose control register. The bits in this register and the corresponding GPE are cleared by writing a 1
to the corresponding bit location. The status bits in this register do not depend upon the states of corresponding bits
in the general-purpose enable register. Access this register only through function 0. See Table 4
–
17 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
General-purpose event status
Type
RC
RC
R
R
RC
R
R
RC
R
R
R
RC
RC
RC
RC
RC
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
General-purpose event status
A8h (function 0)
Read-only, Read/Clear
0000h
Table 4
–
17. General-Purpose Event Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
ZV0_STS
RC
PC Card socket 0 ZV status. Bit 15 is set on a change in status of bit 6 (ZVENABLE) in the function 0 card
control register (PCI offset 91h, see Section 4.32).
14
ZV1_STS
RC
PC Card socket 1 ZV status. Bit 14 is set on a change in status of bit 6 (ZVENABLE) in the function 1 card
control register (PCI offset 91h, see Section 4.32).
13
–
12
RSVD
R
Reserved. Bits 13 and 12 return 0s when read.
11
PWR_STS
RC
Power-change status. Bit 11 is set when software has changed the power state of either socket. A change
in either VCC or VPP for either socket causes this bit to be set.
Reserved. Bits 10 and 9 return 0s when read.
10
–
9
RSVD
R
8
VPP12_STS
RC
12-V VPP request status. Bit 8 is set when software has changed the requested VPP level to or from 12 V
for either of the two PC Card sockets.
7
–
5
RSVD
R
Reserved. Bits 7
–
5 return 0s when read.
4
GP4_STS
RC
GPI4 Status. Bit 4 is set on a change in status of the MFUNC5 terminal input level.
3
GP3_STS
RC
GPI3 Status. Bit 3 is set on a change in status of the MFUNC4 terminal input level .
2
GP2_STS
RC
GPI2 Status. Bit 2 is set on a change in status of the MFUNC2 terminal input level.
1
GP1_STS
RC
GPI1 Status. Bit 1 is set on a change in status of the MFUNC1 terminal input level.
0
GP0_STS
RC
GPI0 Status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.
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