參數(shù)資料
型號(hào): PCI1520-EP
英文描述: Military Enhanced Plastic PC Card Controllers Data Manual
中文描述: 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊(cè)
文件頁(yè)數(shù): 71/125頁(yè)
文件大?。?/td> 716K
代理商: PCI1520-EP
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4
18
Table 4
8. System Control Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
11
PWRSTREAM
R
Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch
is in progress and a powering change has been requested. This bit is cleared when the power stream is
complete.
0 = Power stream is complete and delay has expired.
1 = Power stream is in progress.
Power-up delay in progress status. When set, bit 10 indicates that a power-up stream has been sent to
the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay has
expired.
Power-down delay in progress status. When set, bit 9 indicates that a power-down stream has been sent
to the power switch and proper power may not yet be stable. This bit is cleared when the power-down delay
has expired.
Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when
interrogation completes. This bit is socket dependent.
0 = Interrogation not in progress (default)
1 = Interrogation in progress
Reserved. Bit 7 returns 0 when read.
Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock,
then the applicable CB state machine will not be clocked.
10
DELAYUP
R
9
DELAYDOWN
R
8
INTERROGATE
R
7
RSVD
R
6
PWRSAVINGS
RW
5
SUBSYSRW
RW
Subsystem ID (PCI offset 42h, see Section 4.27), subsystem vendor ID (PCI offset 40H, see
Section 4.26), ExCA identification and revision (ExCA offset 00h/40h/800h, see Section 5.1) registers
read/write enable. Bit 5 is shared by functions 0 and 1.
0 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read/write.
1 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read-only
(default).
CardBus data parity SERR signaling enable
0 = CardBus data parity not signaled on PCI SERR
1 = CardBus data parity signaled on PCI SERR
Reserved. Do not change the default value.
ExCA power-control bit.
0 = Enables 3.3 V
1 = Enables 5 V
Keep clock. This bit works with PCI and CB CLKRUN protocols.
0 = Allows normal functioning of both CLKRUN protocols (default)
1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols
RI_OUT/PME multiplex enable.
0 = RI_OUT and PME are both routed to the RI_OUT/PME terminal. If both functions are are enabled
at the same time, the terminal becomes RI_OUT only and PME assertions are not seen.
1 = Only PME is routed to the RI_OUT/PME terminal.
This bit is global and is accessed only through function 0.
4
CB_DPAR
RW
3
RSVD
RW
2
EXCAPOWER
RW
1
KEEPCLK
RW
0
RIMUX
RW
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