參數(shù)資料
型號(hào)： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊(cè)
文件頁(yè)數(shù)： 63/125頁(yè)
文件大?。?/td> 716K
代理商： PCI1520-EP
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4
–
10
4.18 CardBus Latency Timer Register
This register is programmed by the host system to specify the latency timer for the PCI1520 CardBus interface in units
of CCLK cycles. When the PCI1520 is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins
counting. If the latency timer expires before the PCI1520 transaction has terminated, then the PCI1520 terminates
the transaction at the end of the next data phase. A recommended minimum value for this register is 40h, which allows
most transactions to be completed.
Bit
7
6
5
4
3
2
1
0
Name
CardBus latency timer
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
CardBus latency timer
1Bh (functions 0, 1)
Read/Write
00h
4.19 Memory Base Registers 0, 1
The memory base registers indicate the lower address of a PCI memory address range. These registers are used
by the PCI1520 to determine when to forward a memory transaction to the CardBus bus and when to forward a
CardBus cycle to PCI. Bits 31
–
12 of these registers are read/write and allow the memory base to be located anywhere
in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11
–
0 are read-only and always return 0s. Write
transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows
0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero
for the PCI1520 to claim any memory transactions through CardBus memory windows (that is, these windows are
not enabled by default to pass the first 4 Kbytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Memory base registers 0, 1
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Memory base registers 0, 1
Type
RW
RW
RW
RW
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Memory base registers 0, 1
1Ch, 24h
Read-only, Read/Write
0000 0000h
相關(guān)PDF資料
PDF描述
PCI1620GHK Controller Miscellaneous - Datasheet Reference
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
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